Test Point - STMicroelectronics STEVAL-IME008V1 Wiring Manual And Hardware Reference

STEVAL-IME008V1
U4B
IO_1_L41P_GCLK9_IRDY1_M1RASN
XC6SLX16-2CSG324C
Figure 6. STEVAL-IME008V1 circuit schematic (6 of 16)
FPGA - Bank 1
IO_1_L01N_A24_VREF
IO_1_L01P_A25
IO_1_L29N_A22_M1A14
IO_1_L29P_A23_M1A13
IO_1_L30N_A20_M1A11
IO_1_L30P_A21_M1RESET
IO_1_L31N_A18_M1A12
IO_1_L31P_A19_M1CKE
IO_1_L32N_A16_M1A9
IO_1_L32P_A17_M1A8
IO_1_L33N_A14_M1A4
IO_1_L33P_A15_M1A10
IO_1_L34N_A12_M1BA2
IO_1_L34P_A13_M1WE
IO_1_L35N_A10_M1A2
IO_1_L35P_A11_M1A7
IO_1_L36N_A8_M1BA1
IO_1_L36P_A9_M1BA0
IO_1_L37N_A6_M1A1
IO_1_L37P_A7_M1A0
IO_1_L38N_A4_M1CLKN
IO_1_L38P_A5_M1CLK
IO_1_L39N_M1ODT
IO_1_L39P_M1A3
IO_1_L40N_GCLK10_M1A6
IO_1_L40P_GCLK11_M1A5
IO_1_L41N_GCLK8_M1CASN
IO_1_L42N_GCLK6_TRDY1_M1LDM
IO_1_L42P_GCLK7_M1UDM
IO_1_L43N_GCLK4_M1DQ5
IO_1_L43P_GCLK5_M1DQ4
IO_1_L44N_A2_M1DQ7
IO_1_L44P_A3_M1DQ6
IO_1_L45N_A0_M1LDQSN
IO_1_L45P_A1_M1LDQS
IO_1_L46N_FOE_B_M1DQ3
IO_1_L46P_FCS_B_M1DQ2
IO_1_L47N_LDC_M1DQ1
IO_1_L47P_FWE_B_M1DQ0
IO_1_L48N_M1DQ9
IO_1_L48P_HDC_M1DQ8
IO_1_L49N_M1DQ11
IO_1_L49P_M1DQ10
IO_1_L50N_M1UDQSN
IO_1_L50P_M1UDQS
IO_1_L51N_M1DQ13
IO_1_L51P_M1DQ12
IO_1_L52N_M1DQ15
IO_1_L52P_M1DQ14
IO_1_L53N_VREF
IO_1_L53P
IO_1_L61N
IO_1_L61P
IO_1_L74N_DOUT_BUSY
IO_1_L74P_AWAKE
DocID026791 Rev 2
F16
FPGA_PMOD1_P2
F15 FPGA_PMOD1_P1
C18 FPGA_PMOD1_P4
C17
FPGA_PMOD1_P3
G14 FPGA_PMOD1_P8
F14 FPGA_PMOD1_P7
D18 FPGA_PMOD1_P10
D17 FPGA_PMOD1_P9
G13 FPGA_PMOD2_P2
H12 FPGA_PMOD2_P1
E18
FPGA_PMOD2_P4
E16 FPGA_PMOD2_P3
K13 FPGA_PMOD2_P8
K12
FPGA_PMOD2_P7
F18 FPGA_PMOD2_P10
F17 FPGA_PMOD2_P9
H14
H13
H16
H15
G18
G16
K14 CTRL_LED1
J13
CTRL_LED0
L13 SEL_PROG_PB
L12 FPGA_CLK_66MHZ
K16 START_PB
K15
L16 STOP_PB
L15
H18
FPGA_RESET
H17
J18 FPGA_USER_IO_0
J16
FPGA_USER_IO_1
K18
FPGA_USER_IO_2
K17 FPGA_USER_IO_3
L18 FPGA_USER_IO_4
L17
FPGA_USER_IO_5
M18 FPGA_USER_IO_6
M16 FPGA_USER_IO_7
N18 FPGA_USER_IO_8
N17
FPGA_USER_IO_9
P18 FPGA_USER_IO_10
P17 FPGA_USER_IO_11
N16
FPGA_USER_IO_12
N15 FPGA_USER_IO_13
T18 FPGA_USER_IO_14
T17
FPGA_USER_IO_15
U18 CTRL_LED3
U17 CTRL_LED2
N14
M14
M13
L14
P16
FPGA_DOUT_BUSY
P15 FPGA_AWAKE
Schematic diagrams
FPGA USER I/O
NOT ASSEMBLY
J7
2 1
4 3
6 5
8 7
10 9
12 11
14 13
16 15
18 17
20 19
22 21
24 23
26 25
28 27
30 29
32 31
HEADER 16X2
TP1

TEST POINT

FPGA_MCU_AWAKE
GSPG30072014DI1205
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