Fpga Configuration - STMicroelectronics STEVAL-IME008V1 Wiring Manual And Hardware Reference

STEVAL-IME008V1
Figure 10. STEVAL-IME008V1 circuit schematic (10 of 16)

FPGA CONFIGURATION

+VFPGA_IO_3V3
R16
10K 0402
FPGA_INIT_B
FPGA_MODE0
FPGA_MODE1
Configuration mode selection:
FPGA_MODE0 = Parallel (Low) or Serial (High)
FPGA_MODE1 = Master (Low) or Slave (High)
When FPGA_INIT_B (bidirectional open-drain) is Low the configuration memory is
being cleared.
When held Low, the start of configuration is delayed.
During configuration, a Low on this output indicates that a
error has occurred.
SPI FLASH CTRL SIGNALS
Place R38 close to the FPGA device
R38
CCLK
FPGA_SPI_MISO1
FPGA_SPI_MOSI
FPGA_SPI_SEL
FPGA_SPI_MISO2
FPGA_SPI_MISO3
TO CORRECT
J10
1
2
3
4
5
6
7
8
9
10
CON10 R127
56
EXT SPI
FLASH
D29
Place D29
GREEN
close to J10
DocID026791 Rev 2
R17 R18
2K43 0402 DNP
2K43 0402
R21
2K43 0402 DNP
33R2 0402
+VFPGA_IO_3V3
C33 C34
10uF 10V 0805 100nF
C33 Details:
TDK (C2012X7R1A106K) - DIGIKEY (445-6857-2-ND)
Dimension 0805 - EIA 2012
Schematic diagrams
MCU_FPGA_INIT_B
MCU_FPGA_MODE1
R22
2K43 0402
configuration data
FPGA_SPI_CCLK
FPGA_SPI_MISO1
FPGA_SPI_MOSI
FPGA_SPI_SEL
FPGA_SPI_MISO2
FPGA_SPI_MISO3
MCU_FPGA_PROG
R39
NA 0402
R40
NA 0402
GSPG30072014DI1230
11/19
19