M.2 Connectivity Slot: Key E Socket 1 - Seco SBC Series User Manual

3.3.13 M.2 Connectivity Slot: Key E Socket 1

M.2 Connectivity Slot: Socket 1 Key E type 2230 - CN16
Pin Signal Pin
1 GND
3 USB_P4+
5 USB_P4-
7 GND
9 ---
11 ---
13 ---
15 ---
17 ---
19 ---
21 ---
23 ---
33 GND
35 PCIe2_Tx+
37 PCIe2_Tx-
39 GND
41 PCIe2_Rx+
43 PCIe2_Rx-
45 GND
47 PCIe2_CLK+
49 PCIe2_CLK-
51 GND
53 PCIe_REQ2#
55 M.2_WAKE#
57 GND
SBC-A80-eNUC
SBC-A80-eNUC User Manual - Rev. First Edition: 1.0 - Last Edition: 1.2 - Author: S.B. - Reviewed by G.G Copyright © 2017 SECO S.r.l.
Signal
2 +3.3V_A
4 +3.3V_A
6 ---
8 ---
10 ---
12 ---
14 ---
16 ---
18 GND
20 ---
22 ---
32 ---
34 ---
36 ---
38 ---
40 ---
42 ---
44 ---
46 ---
48 ---
50 SUS_CLK
52 PLT_RST#
54 BT_DISABLE#
56 WIFI_DISABLE
58 M.2_I2C_SDA
It is possible to increase the connectivity of the SBC-A80-
eNUC board by using M.2 Socket 1 Key E connectivity
modules.
The connector used for the M.2 Connectivity slot is CN16,
which is a standard 75 pin M.2 Key E connector, type
LOTES p/n APCI0076-P001A, H=4.2mm, with the pinout
shown in the table on the left.
On the SBC-A80-eNUC board there is also a Threaded Spacer which allows the placement
of M.2 Socket 1 Key E connectivity modules in 2230 size.
Here following the signals related to this connectivity interface:
USB_P4+/USB_P4-: USB 2.0 Port #4 differential pair.
PCIe2_TX+/PCIe2_TX-: PCI Express lane #2, Transmitting Output Differential pair
PCIe2_RX+/PCIe2_RX-: PCI Express lane #2, Receiving Input Differential pair
PCIe2_Clock+ / PCIe2_Clock-: PCI Express Reference Clock for lane #2, Differential Pair
M.2_WAKE#: Board's Wake Input, 3.3V_A active low signal. It must be externally driven by
the Connectivity module inserted in the slot when it requires waking up the system.
PLT_RST#: Reset Signal that is sent from the SoC to all PCI-e devices available on the board
(i.e. the GbE controllers) and on the connectivity module. It is a 3.3V active-low signal.
PCIe_REQ2#: PCI Express Clock Request Input, active low signal. This signal shall be driven
low by any module inserted in the connectivity slot, in order to ensure that the SoC makes
available the reference clock.
SUS_CLK: 32.768kHz Clock provided by the SBC-A80-eNUC board to the module plugged
in the slot CN17. +3.3V_A electrical level.
BT_DISABLE#: Bluetooth module disable, active low signal, +3.3V_A electrical level. This
signal can be used to disable Bluetooth functionalities of any connectivity module plugged in
CN16 Slot. This signal is also managed by BIOS (see par. 4.5, "Bluetooth on M.2").
WIFI_DISABLE#; WiFi module disable, active low signal, +3.3V_A electrical level. This signal
can be used to disable WiFi functionalities of any connectivity module plugged in CN16 Slot.
This signal is also managed by BIOS (see par. 4.5, "WiFi on M.2")
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