Table 2.15:Pcie Devices - Advantech FWA-1320 User Manual

2.4.8.3 PCIe Tree
The BIOS also performs an enumeration of all PCIe resources, builds a bus/device
map and assigns resources to the PCIe devices. Most OSes perform a reallocation of
resources during start up. However, the PCIe bus/device map will not be changed by
the OS. The table below gives an overview of the PCIe devices and their correspond-
ing system function:
Table 2.15: PCIe Devices
PCIe bus:
dev:fun
00:00:00
00:01:00
00:02:00
00:02:00
00:0b:00
00:0e:00
00:0f:00
00:13:00
00:14:00
00:14:01
00:14:02
00:14:03
00:16:00
00:17:00
00:18:00
00:1f:00
00:1f:03
02:00:00
03:00:00
PCIe VenID:
Device
DevID
8086:1f0b Host bridge
8086:1f10 PCI bridge
8086:1f11 PCI bridge
8086:1f12 PCI bridge
8086:1f18 Co-processor
8086:1f14 Host bridge
8086:1f16 IOMMU
System periph-
8086:1f15
eral
Ethernet control-
8086:1f41
ler
Ethernet control-
8086:1f41
ler
Ethernet control-
8086:1f41
ler
Ethernet control-
8086:1f41
ler
8086:1f2c USB controller
8086:1f22 SATA controller
8086:1f32 SATA controller
8086:1f38 ISA bridge
8086:1f3c S
MBus
Ethernet control-
8086:1533
ler
Ethernet control-
8086:1533
ler
Description
Intel Atom C2000 SoC Transaction
Router
Intel Atom C2000 PCIe Root Port 1
Intel Atom C2000 PCIe Root Port 2
Intel Atom C2000 PCIe Root Port 3
Intel Atom C2000 nCPM for QuickAssist
Technology
Intel Atom C2000 RAS
Intel Atom processor RCEC
Intel Atom C2000 SMBus 2.0 Controller
Intel I354 connected to traffic port
labelled "1"
Intel I354 connected to traffic port
labelled "2"
Intel I354 connected to traffic port
labelled "3"
Intel I354 connected to traffic port
labelled "4"
Intel Atom C2000 USB Enhanced Host
Controller
Intel Atom C2000 AHCI SATA2 Control-
ler
Intel Atom C2000 AHCI SATA3 Control-
ler
Intel Atom C2000 PCU Legacy Bus
Bridge (LPC, legacy devices)
Intel Atom C2000 PCU SMBus
(SMBus Controller 0)
Intel I210 connected to management
port labelled "MGT0"
Intel I210 connected to management
port labelled "MGT1"
27 FWA-1320 User Manual