Texas Instruments TMS320C6000 Reference Manual page 223

G
H
I
global interrupt enable bit (GIE): A bit in the control status register (CSR)
that is used to enable or disable maskable interrupts.
HAL: Hardware abstraction layer of the CSL. The HAL underlies the service
layer and provides it a set of macros and constants for manipulating the
peripheral registers at the lowest level. It is a low-level symbolic interface
into the hardware providing symbols that describe peripheral registers/
bitfields and macros for manipulating them.
host: A device to which other devices (peripherals) are connected and that
generally controls those devices.
host port interface (HPI): A parallel interface that the CPU uses to commu-
nicate with a host processor.
HPI: See host port interface ; see also HPI module .
HPI module: HPI is an API module used for configuring the HPI registers.
Functions are provided for reading HPI status bits and setting interrupt
events.
index: A relative offset in the program address that specifies which of the
512 frames in the cache into which the current access is mapped.
indirect addressing: An addressing mode in which an address points to
another pointer rather than to the actual data; this mode is prohibited in
RISC architecture.
instruction fetch packet: A group of up to eight instructions held in memory
for execution by the CPU.
internal interrupt: A hardware interrupt caused by an on-chip peripheral.
Glossary
Glossary A-5