HMCBSP
5.9.5
HMCBSP_XCR
(RW) HMCBSP_XCR0
(RW) HMCBSP_XCR1
(RW) HMCBSP_XCR2*
Fields
(RW) HMCBSP_XCR_XWDREVRS
(RW) HMCBSP_XCR_XWDLEN1
(RW) HMCBSP_XCR_XFRLEN1
(RW) HMCBSP_XCR_XPHASE2
(RW) HMCBSP_XCR_XDATDLY
(RW) HMCBSP_XCR_XFIG
(RW) HMCBSP_XCR_XCOMPAND
(RW) HMCBSP_XCR_XWDLEN2
(RW) HMCBSP_XCR_XFRLEN2
(RW) HMCBSP_XCR_XPHASE
* only on devices with three or more serial ports
5.9.6
HMCBSP_SRGR
(RW) HMCBSP_SRGR0
(RW) HMCBSP_SRGR1
(RW) HMCBSP_SRGR2*
Fields
(RW) HMCBSP_SRGR_CLKGDV
(RW) HMCBSP_SRGR_FWID
(RW) HMCBSP_SRGR_FPER
(RW) HMCBSP_SRGR_FSGM
(RW) HMCBSP_SRGR_CLKSM
(RW) HMCBSP_SRGR_CLKSP
(RW) HMCBSP_SRGR_GSYNC
* only on devices with three or more serial ports
5-36
transmit control register
32-bit reversal feature
element length in phase 1
frame length in phase 1
phase 2
data delay
frame ignore
companding mode
element length in phase 2
frame length in phase 2
phases
sample rate generator register
clock divider
frame width
frame period
transmit frame sync mode
clock mode
CLKS polarity clock edge select
clock sync
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