Texas Instruments TMS320C6000 Reference Manual page 191

5.4.3
HDMA_SECCTL
(RW) HDMA_SECCTL0*
(RW) HDMA_SECCTL1*
(RW) HDMA_SECCTL2*
(RW) HDMA_SECCTL3*
Fields
(RW) HDMA_SECCTL_SXCOND
(RW) HDMA_SECCTL_SXIE
(RW) HDMA_SECCTL_FRAMECOND frame complete condition
(RW) HDMA_SECCTL_FRAMEIE
(RW) HDMA_SECCTL_LASTCOND
(RW) HDMA_SECCTL_LASTIE
(RW) HDMA_SECCTL_BLOCKCOND block transfer complete condition
(RW) HDMA_SECCTL_BLOCKIE
(RW) HDMA_SECCTL_RDROPCOND dropped read synchronization condition
(RW) HDMA_SECCTL_RDROPIE
(RW) HDMA_SECCTL_WDROPCOND dropped write synchronization condition
(RW) HDMA_SECCTL_WDROPIE
(RW) HDMA_SECCTL_RSYNCSTAT read synchronization status
(RW) HDMA_SECCTL_RSYNCCLR
(RW) HDMA_SECCTL_WSYNCSTAT write synchronization status
(RW) HDMA_SECCTL_WSYNCCLR
(RW) HDMA_SECCTL_DMACEN
(RW) HDMA_SECCTL_FSIG
(RW) HDMA_SECCTL_RSPOL
(RW) HDMA_SECCTL_WSPOL
* only supported on devices with DMA
5.4.4
HDMA_SRC
(RW) HDMA_SRC0*
(RW) HDMA_SRC1*
(RW) HDMA_SRC2*
(RW) HDMA_SRC3*
Fields
(RW) HDMA_SRC_SRC
* only supported on devices with DMA
DMA secondary control register
split transfer overrun receive condition
split transfer overrun receive interrupt en-
able
frame complete interrupt enable
last frame condition
last frame interrupt enable
block transfer complete interrupt enable
dropped read synchronization interrupt en-
able
dropped write synchronization interrupt en-
able
read synchronization status clear
write synchronization status clear
DMAC pin control
frame sync ignore
read sync polarity
write sync polarity
DMA source address register
source address
HDMA
HAL Reference 5-15