4.8.7
EMIF_MK_SDEXT
Macro
Arguments
Makes a value suitable for the EMIF SDRAM extension
register
EMIF_MK_SDEXT(
tcl,
tras,
trrd,
twr,
thzp,
rd2rd,
rd2deac,
rd2wr,
r2wdqm,
wr2wr,
wr2deac,
wr2rd
)
tcl
tras
trrd
twr
thzp
rd2rd
rd2deac
rd2wr
r2wdqm
wr2wr
SDRAM CAS latency:
EMIF_SDEXT_TCL_OF(x)
SDRAM Tras value:
EMIF_SDEXT_TRAS_OF(x)
SDRAM Trrd value:
EMIF_SDEXT_TRRD_OF(x)
SDRAM Twr value:
EMIF_SDEXT_TWR_OF(x)
SDRAM Thzp value:
EMIF_SDEXT_THZP_OF(x)
Read to read clocks:
EMIF_SDEXT_RD2RD_OF(x)
Read to DEAC clocks:
EMIF_SDEXT_RD2DEAC_OF(x)
Read to write cycles:
EMIF_SDEXT_RD2WR_OF(x)
BEx high clocks:
EMIF_SDEXT_R2WDQM_OF(x)
Write to write clocks:
EMIF_SDEXT_WR2WR_OF(x)
CSL API Reference
EMIF
4-77
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