Cypress CY8CKIT-059 PSoC 5LP Prototyping Kit Manual page 40

KP_VDD
KP_VDDIO0
KP_VDDIO1
KP_VDDIO2
KP_VDDIO3
C11 C1 C3 C14
0.1 uF
0402 0.1 uF 0402 0.1 uF 0402 0.1 uF 0402
KP_VDD
VDDD
C24 C5
0603 1.0 uF 0402 0.1 uF
VDDD
C25 C6
0603 0402
1.0 uF 0.1 uF
VDDA
C39
C38
0402 0603
0.1 uF 1.0 uF
VCCA
C30
1.0 uF
0603
KP_VCCD
C10 C28
0402
0.1 uF 1.0 uF
J10
1
VBUS
2 KP_DM
DM
3 KP_DP
DP
4
GND
USB FINGER
USB Finger Connector
CY8CKIT-059 PSoC® 5LP Prototyping Kit Guide, Doc. #: 001-96498 Rev. *G
Kitprog on-board Programmer / Debugger
U1
KP_P2_6 1
P2_6
KP_P2_7 2
P2_7
KP_P12_4 3
P12_4 I2C0_SCL, SIO
KP_P12_5 4
P12_5 I2C0_SDA, SIO
5
VSSB
6
IND
7
VBOOST
8 CY8C5868LTI-LP039 QFN68
VBAT
VSSD 9
VSSD
KP_XRES 10
XRES
11
P1_0
12
P1_1
13
P1_2 SIO, I2C1_SDA P12_1
14
P1_3 SIO, I2C1_SCL P12_0
15
P1_4
16
P1_5
KP_VDDIO1 17
VDDIO1
KP_VDD VTARG VBUS
Place Near PSoC 5LP
R2
R1 R3
15K
4.7K 15K
KP_P1_6
No Load
KP_P1_7
KP_XRES
C2 R14 R13
30K 30K
0402 0.1 uF
No Load
VBUS
J7
F2 1
1
2
2
3
3
PTC Resettable Fuse 4
4
5
5
C40
0.1 uF HDR 1x5
0402
No Load
Target PSoC Program/Debug Header
KP_VDD
R8
ZERO
VTARG
D1
51 KP_P0_3
P0_3
50 KP_P0_2
P0_2
49 KP_P0_1
P0_1
48 KP_P0_0
P0_0
47 KP_P12_3
SIO_P12_3
46 KP_P12_2
SIO_P12_2 KP_P0_4
45 VSSD
VSSD KP_P0_3
44 VDDA
KP_P0_2
VDDA
43
VSSA
42 VCCA
C15 C16 C8
VCCA
41
P15_3
40
P15_2 0603 1.0 uF 0603 1.0 uF 1.0 uF
39 KP_P12_1
38 KP_P12_0
37
P3_7
36 KP_P3_6
P3_6
35 KP_VDDIO3
VDDIO3
P3_3, P3_2, P0_7, P0_6, P0_5, P0_4
pins are reserved for HW REV ID
5(MSB) 4 3 2 1
P3.3 P3.2 P0.7 P0.6 P0.5
Floating GND Floating Floating GND
GND read as binary "1"
floating pin is read as binary "0"
VTARG
KP_P12_4
PROG_RESET
KP_P12_3
PROG_SWDCLK
KP_P12_2
PROG_SWDIO
PCA:
PCB:
FAB DRW:
ASSY DRW: 620-60243-01
SCH:
LED3
820 ohm
R21
KP_P3_1 2 1
0805
Status LED Green
Status LED
VBUS
VBUS
LED2
560 ohm
R10 2 1
0805
VBUS
POWER LED Amber
Power LED
SW3
PROG_RESET 1A 2A
1B 2B
Switch
SAR Bypass
Capacitor
VTARG
KP_P2_6
KP_P2_7
R9 R7
2.2K 2.2K
U3
NTZD3152P
0(LSB)
P0.4
KP_P12_1
Floating KP_P12_0
KP_P12_7
UART TX
KP_P12_6
UART RX
I2C & UART Connection
VBUS
J9
1
KP_P3_0
2
KP_P12_5 KP_P3_4
3
I2C_SCL KP_P3_5
4
I2C_SDA KP_P3_6
5
UART RX KP_P0_0
6
UART TX KP_P0_1
7
HDR 1x7 HDR 1x7
No Load
KitProg I/O Headers
CYPRESS SEMICONDUCTOR © 2015 CYPRESS SEMICONDUCTOR © 2015 CYPRESS SEMICONDUCTOR © 2015
121-60210-01
Title Title Title
600-60243-01
CY8CKIT-059 PSoC 5LP Prototyping Kit CY8CKIT-059 PSoC 5LP Prototyping Kit CY8CKIT-059 PSoC 5LP Prototyping Kit
610-60235-01
Size Size Size Document Number Document Number Document Number
630-60242-01 630-60242-01 630-60242-01
B B B
630-60242-01
I2C_SDA
I2C_SCL
J8
1
2
3
4
5
6
7
No Load
Rev Rev Rev
06 06 06
40