Appendix; Psoc 5Lp Prototyping Kit Schematics - Cypress CY8CKIT-059 PSoC 5LP Prototyping Kit Manual

A.

Appendix

A.1

PSoC 5LP Prototyping Kit Schematics

J1
1 P2_0
1
2 P2_1
2
3 P2_2
3
4 P2_3
4
5 P2_4
5
6 P2_5
6
P2_6
7
7
8 P2_7
8
9 P12_7 provide silk
UART TX
9
10 P12_6 for UART pins
UART RX
10
11 P12_5
11
12 P12_4
12
13 P12_3
13
14 P12_2
14
15 P12_1 I2C_SDA provide silk
15
16 P12_0 I2C_SCL for I2C pins
16
17 P1_0
17
18 P1_1
18
19 P1_2
19
P1_3
20
20
21 P1_4
21
22 P1_5
22
23 P1_6
23
24 P1_7
24
25
25
26 VDDIO
26
HDR 1x26
No Load
PSoC 5LP I/O Header
VDD
VDD
VDDA
C22 C26 C21
C36 C34
0402 0603 0603 0402
0.1 uF 1.0 uF
1.0 uF 0603 0402 0.1 uF 1.0 uF
VCCA
P_VCCD
P_VCCD
C37
C31
1.0 uF
0603 C29
0603
1.0 uF
0.1 uF
0402
VTARG
J3
1
1
2
2
3
PROG_RESET
3
4
PROG_SWDCLK
4
5
PROG_SWDIO
5
HDR 1x5
I2C_SCL
No Load I2C_SDA
R22 0603
UART RX
R23 0603
UART TX
This signals will be coming from Kitprog from Breakable area
CY8CKIT-059 PSoC® 5LP Prototyping Kit Guide, Doc. #: 001-96498 Rev. *G
PSoC 5LP Target Device
U2
P2_6 1
P2_6
P2_7 2
P2_7
P12_4 3
P12_4 I2C0_SCL, SIO
P12_5
4
P12_5 I2C0_SDA, SIO
5
VSSB
6
IND
7
VBOOST
8 CY8C5888LTI-LP097 QFN68
VBAT
VSSD 9
VSSD
PROG_RESET XRES 10
XRES
PROG_SWDIO P1_0 11
P1_0
PROG_SWDCLK P1_1 12
P1_1
P1_2 13
P1_2
P_SWO P1_3 14
P1_3
P_TDI P1_4 15
P1_4
P1_5 16
P1_5
VDDIO1 17
VDDIO1
VDDD
C23
0.1 uF
DP R16 22E
DM R17 22E
VTARG
C33
0402 0.1 uF
PSoC 5LP Program/Debug Header
USB Connector
J6
USB Micro-B
1
VBUS
2 DM
DM
3 DP
DP
4
ID
5
GND
100K R12
ZERO P12_7 UART TX
ZERO P12_6
UART RX
C19 0.01 uF
VDDIO0
VDDIO1
VDDIO2
VDDIO3
51 P0_3
P0_3
50 P0_2
P0_2
49 P0_1
P0_1
P0_0
48
P0_0
47 P12_3
SIO_P12_3
46 P12_2
SIO_P12_2
45 VSSD
VSSD
44 VDDA
VDDA
43 VSSA
VSSA
42 VCCA
VCCA
41 P15_3
P15_3
40 P15_2
P15_2
39 P12_1
SIO, I2C1_SDA P12_1
38 P12_0
SIO, I2C1_SCL P12_0
37 P3_7
P3_7
36 P3_6
P3_6
35 VDDIO3
VDDIO3
P15_4
J5
PROG_SWDIO
1 2
PROG_SWDCLK
3 4
P_SWO
5 6
P_TDI
7 8
PROG_RESET
9 10
50MIL KEYED SMD
No Load
F1 D2 VTARG P15_2
SOD123
C27
PTC Resettable Fuse
0.1 uF
0402 P15_3
TP1 TP2 TP3
BLACK BLACK BLACK
0402
No Load No Load No Load
VDDIO
C32 C20 C18 C35
0402 0402 0402 0402
0.1 uF 0.1 uF 0.1 uF 0.1 uF
P0_4
P0_3
P0_2
C9
P3_2
SAR0 EXTREF
0603
1.0 uF
C13
EXTREF0
1.0 uF
0603
C12
PSoC 5LP I/O Header
SAR1 EXTREF
0603 1.0 uF
C7
EXTREF1
0603
1.0 uF
P2_1
SAR Bypass Capacitors
USER LED
P2_2
R5
CMOD
0603
C4
ZERO
VTARG
2200 pF
R19
4.7K
No Load
XRES
C17
0.1 uF
0402
No Load
VTARG
Y1
R20 ZERO
2 1
32.768 KHz
No Load
C42
C41 J4
22 pF
22 pF
0402
No Load HEADER 1X 2
CYPRESS SEMICONDUCTOR © 2015 CYPRESS SEMICONDUCTOR © 2015 CYPRESS SEMICONDUCTOR © 2015
Title Title Title
PCA: 121-60210-01
CY8CKIT-059 PSoC 5LP Prototyping Kit CY8CKIT-059 PSoC 5LP Prototyping Kit CY8CKIT-059 PSoC 5LP Prototyping Kit
PCB: 600-60243-01
FAB DRW: 610-60235-01
Size Size Size Document Number Document Number Document Number
ASSY DRW: 620-60243-01 630-60242-01 630-60242-01 630-60242-01
B B B
SCH: 630-60242-01
Date: Date: Date: Tuesday, June 16, 2015 Tuesday, June 16, 2015 Tuesday, June 16, 2015
J2 VDD
1
1
2
2
3 XRES
3
4 P0_7
4
P0_6
5
5
6 P0_5
6
7 P0_4 P3_2,P0_2, P0_3 and P0_4
7
8 P0_3 these pins
8
have bypass CAP
9 P0_2
9
connected
10 P0_1
10
11 P0_0
11
12 P15_5
12
13 P15_4
13
14 P15_3
14
15 P15_2
15
16 P15_1
16
17 P15_0
17
P3_7
18
18
19 P3_6
19
20 P3_5
20
21 P3_4
21
22 P3_3
22
23 P3_2
23
24 P3_1
24
25 P3_0
25
26
26
HDR 1x26
No Load
LED1
820 ohm
R18
2 1
0805
User LED BLUE
SW1
1A 2A
1B 2B
Switch
USER PUSH BUTTON
SW2
XRES 1 2
SW PUSHBUTTON
No Load
P5LP_VDD VDD
P5LP_VDD
R11
ZERO
P5LP_VDD
VDDIO
R15 ZERO
Rev Rev Rev
06 06 06
Sheet Sheet Sheet 2 2 2 of of of 3 3 3
39