Spi Timing Characteristics - Atmel ATmega48/V Preliminary

26.7

SPI Timing Characteristics

ATmega48/88/168
304
Figure 26-4. 2-wire Serial Bus Timing
SCL
t
SU;STA
SDA
See Figure 26-5 and Figure 26-6
Table 26-3. SPI Timing Parameters
Description
1 SCK period
2 SCK high/low
3 Rise/Fall time
4 Setup
5 Hold
6 Out to SCK
7 SCK to out
8 SCK to out high
9 SS low to out
10 SCK period
(1)
11 SCK high/low
12 Rise/Fall time
13 Setup
14 Hold
15 SCK to out
16 SCK to SS high
17 SS high to tri-state
18 SS low to SCK
Note: 1. In SPI Programming mode the minimum SCK high/low period is:
- 2 t for f
CLCL CK
- 3 t for f
CLCL CK
2. All DC Characteristics contained in this datasheet are based on simulation and characteriza-
tion of other AVR microcontrollers manufactured in the same process technology. These
values are preliminary values representing design targets, and will be updated after character-
ization of actual silicon.
t
HIGH
t
of
t t
LOW LOW
t t
HD;STA HD;DAT
for details.
Mode Min
Master
Master
Master
Master
Master
Master
Master
Master
Slave
Slave 4 • t
ck
Slave 2 • t
ck
Slave
Slave 10
Slave t
ck
Slave
Slave 20
Slave
Slave 20
< 12 MHz
> 12 MHz
t
r
t
SU;DAT
t
SU;STO
Typ Max
See Table 16-4
50% duty cycle
3.6
10
10
0.5 • t
sck
10
10
15
1600
15
10
t
BUF
ns
2545E–AVR–02/05