Mc6805R3/Mc6805U3 Timer Circuitry - Motorola MC6805R Series Advance Information

decrement the timer prescaler. The maximum frequency of a signal that can be recognized by the
TIMER pin logic is dependent on the parameter labeled tWL tWH. The pin logic that recognizes the
high state on the pin must also recognize the low state on the pin in order to "re-arm" the internal
logic. Therefore, the period can be calculated as follows (assumes 50/50 duty cycle for a given
period):
tcyc x 2
+
250 ns
=
period
=
- f 1
req
The period is not simply tWL
+
tWH. This computation is allowable, but it does reduce the maxi-
mum allowable frequency by defining an unnecessarily longer period (250 nanoseconds times two).
When the phase two signal is used as the source, it can be gated by an input applied to the TIMER
input pin allowing the user to easily perform pulse-width measurements. The source of the clock in-
put is one of the mask options that is specified before manufacture of the MCU.
NOTE
For ungated phase two clock input to the timer prescaler, the TI M ER pin should be tied to
VCC·
A prescaler option, divide by 2n, can be applied to the clock input that extends the timing interval
up to a maximum of 128 counts before decrementing the counter. This prescaling mask option is
also specified before manufacture. To avoid truncation errors, the prescaler is cleared when bit 3 of
the timer control register is written to a logic one (this bit always reads a logic zero).
The timer continues to count past zero, falling through to $FF from $00 and then continuing the
countdown. Thus, the counter can be read at any time by
readin~
the timer data register (TDR).
This allows a program to determine the length of time since a timer interrupt has occurred, and not
disturb the counting process.
At power up or reset, the prescaler and counter are initialized with all logic ones; the timer interrupt
request bit (bit 7) is cleared and the timer interrupt mask bit (bit 6) is set.
S.2 MC680SR3/MC680SU3 TIMER CIRCUITRY
The timer circuitry for the MC6805R31 MC6805U3 microcomputers is shown in Figure 5-2. The timer
contains a single 8-bit software programmable counter with 7-bit software selectable prescaler. The
counter may be preset under program control and decrements toward zero. When the counter
decrements to zero, the timer interrupt request bit, i.e., bit 7 of the timer control register (TCR), is
set. Then if the timer interrupt is not masked, i.e., bit 6 of the TCR and the I bit in the condition
code register are both cleared, the processor receives an interrupt. After completion of the current
instruction, the processor proceeds to store the appropriate registers on the stack, and then fetches
the timer interrupt vector from locations $FF8 and $FF9 in order to begin servicing the interrupt.
The counter continues to count after it reaches zero, allowing the software to determine the num-
ber of internal or external input clocks since the timer interrupt request bit was set. The counter may
be read at any time by the processor without disturbing the count. The contents of the counter
become stable prior to the read portion of a cycle and do not change during the read. The timer in-
terrupt request bit remains set until cleared by the software. If a write occurs before the timer inter-
rupt is serviced, the interrupt is lost. TCR7 may also be used as a scanned status bit in a non-
interrupt mode of operation (TCR
=
1).
5-2