Motorola MC6805R Series Advance Information page 13

TIMER
PAO
PAl
Accumulator
Port
PA2
Data
8
A
CPU
A
PA3
Dir
Index Control
1/0
PA4
Reg
Register
PDO/ANO
Lines
PA5
8
X PD1/ANl
PA6
Condition
PD2/AN2
Port
PAl
Code
PD3/AN3
D
Register
CC
PD4IVRL Input
CPU
PD5IVRH Lines
Stack
PD6/iNTI
PBO
Pointer
SP
PDl
PBl
Program
Port
PB2
Port
Data
Counter
B
PB3
1/0
B
Dir
4
High
PCH
ALU
PB4
Reg
Reg
Lines
PB5
Program
PB6
Counter
PBl
8 Low
PCO
PCl
PC2
Port
PC3
C
PC4
1/0
PC5 Lines
PC6
PCl
Figure 1-1. MC6805R2 Block Diagram
TIMER
PAO
PAl
Accumulator
Port
PA2
Data
A
iN'f2
CPU
A
PA3
Dir
Index Control
1/0
PA4
Reg
Lines
PA5
Register
PD~
X
PA6
PDl
PA7
Condition
PD2
Code
PD3
Port D
Register
CC
Input
CPU
PD4
Lines
Stack PD5
PBO
Pointer
PD6/1NT2
SP
PD7
PBl
Program
Port
PB2
B
Port Data
Counter
PB3
B Dir
High
PCH
1/0
PB4
ALU
Lines
PB5
Reg
Reg
Program
PB6
Counter
PB7
8
Low PCO
PCl
Data
Port
.PC2
Port
Dir C
PC3
C
Reg
Reg
PC4
1/0
PC5
Lines
PC6
PC7
Figure 1-2. MC6805U2 Block Diagram
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