Motorola MC6805R Series Advance Information page 14

TIMER
PAO
PA1
Accumulator
Port
PA2
Data
A
A
PA3
CPU
Dir
Index Control
1/0
PA4
Reg
Register
PDO/ANO
Lines
PA5
X PD1/AN1
PA6
Condition
PD2/AN2
Port
PAl
Code
PD3/AN3
D
PD4/VRL
Input
Register
CC
CPU
PD5IVRH Lines
Stack
PD6/~
PBO
Pointer
SP
PD?
PB1
Program
Port
PB2
B
Data
Counter
PB3
Dir
High
PCH
1/0
PB4
. ALU
Lines
PB5
Reg
Program
PB6
Counter
PB?
Low
PCO
PC1
Data Port
PC2
Port
Dir C
PC3
C
Reg Reg
PC4
1/0
PC5
Lines
PC6
PC?
Figure 1-3, MC6805R3 Block Diagram
RESET INT
TIMER
Accumulator
Port
Data
A
CPU
INT2
A
Dir
Index Control
1/0
Reg
Register
Lines
PD~
X
P01
Condition
PD2
Code
Port D
~D3
Port D
Register
CC Input
Input
CPU PD4
Lines
Stack
PD5 _
PBO
Pointer
SP
PD6(1NT2
PD?
PB1
Program
Port
PB2
Port Data
Counter
B
PB3
B Dir
High
PCH
1/0
PB4
Reg
Reg
ALU
Lines
PB5
Program
PB6
Counter
PB?
Low
PCO
PC1
Data Port
PC2
Port
Dir C
PC3
C
Reg
Reg
PC4
1/0
PC5 Lines
PC6
PC?
Figure 1-4. MC6805U3 Block Diagram
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