Motorola MC6805R Series Advance Information page 22

3.4 MC6805R3 MEMORY MAP
The memory map for the MC6805R3 is shown in Figure 3-4 and is identical to the MC6805U3 except
that two additional registers, the analog-to-digital control register and the analog-to-digital result
register, have been added at locations $OOE and $OOF, respectively.
000
127
128
3895
3896
4087
4088
4089
4090
Interrupt 4091
Vectors 4092
4093
4094'
4095
7
o
1/0 Ports
Timer
RAM
(128 Bytes)
Main User
ROM
(3768 Bytes)
Self Check
ROM
(192 Bytes)
Timer Interrupt
- - - - - - -
External Interrupt
- - -
--
-
-
SWI
- -
- --
- -
RESET
7 6 5 4 3 2 1 0
$000
0
Port A Data Register
1
Port B Data Register
$07F
2
Port C Data Register
$080
3
Port D Data Register
4
PortA DDR*
5
Port B DDR*
6
Port C DDR*
7
Not Used
8
Timer Data Register
9
Timer Control Register
10
Miscellaneous Register
$F37
11
Not Used
$F38
(3 Bytes)
13
14
AI
D Control Register
$FF7
15
AID Result Register
$FF8
16
$FF9
RAM
$FFA
(112 Bytes)
$FFB
$FFC
Stack
$FFD
(31 Bytes Maximum)
$FFE
$FFF
t
127
* Caution: Data direction registers (DDRs) are write-only; they read as $FF.
Figure 3-4. MC6805R3 Memory Map
3-4
$000
$001
$002
$003
$004*
$005*
$006*
$007
$008
$009
$OOA
$OOB
$ooD
$OOE
$OOF
$010
$07F