Version 1.0
Table of Contents
Revision History.......................................................................................................... 2
Table of Contents ....................................................................................................... 3
Table of figures........................................................................................................... 4
Contacting Sundance. ................................................................................................ 5
Notes. ......................................................................................................................... 5
Precautions................................................................................................................. 5
Block Diagram. ........................................................................................................... 7
Architecture Description. ............................................................................................ 8
Virtex FPGA. ........................................................................................................... 9
SHB. ..................................................................................................................... 10
Memory. ................................................................................................................ 10
Clock management. .............................................................................................. 11
TTL I/Os. ............................................................................................................... 11
External triggering. ................................................................................................ 11
ADCs and DAC. .................................................................................................... 11
LEDs. .................................................................................................................... 12
Sundance Standards. ............................................................................................... 12
Communication Ports............................................................................................ 12
ADC Performance. ................................................................................................... 14
DAC Performance. ................................................................................................... 16
SHB pinout. .............................................................................................................. 18
FPGA Pinout............................................................................................................. 19
Connector position.................................................................................................... 24
Operating conditions................................................................................................. 25
Safety.................................................................................................................... 25
EMC ...................................................................................................................... 25
General Requirements .......................................................................................... 25
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SMT370v2 User Manual