Details Of Registers; Enxtncr] (Enc Control Register) - Toshiba TXZ Series Reference Manual

4.2. Details of Registers

For a special description in an operation mode is shown separately after [xx mode] ("xx mode" means the
corresponding operation mode).

4.2.1. [ENxTNCR] (ENC Control Register)

Bit Bit Symbol
31:29 -
28 CMPSEL
27:26 UDMD[1:0]
2018-10-11
After Reset Type
0 R Read as "0".
[Timer mode]
Counter clear condition
0: [ENxINT] register match
1: [ENxRELOAD] register match
When <CMPSEL>=<TOVMD>=1, the counter is not cleared.
0 R/W
[Encoder mode, Sensor mode (Phase count), and Phase
counter mode]
[ENxRELOAD] register match at CW rotation, regardless of the
setting of this bit
[Sensor mode (Event count and Timer count)]
The counter is not cleared by any comparison matches.
[Sensor mode (Phase count), Phase counter mode (Phase
measurement)]
Up-count or Down-count control
00: Up-count
01: Down-count
10, 11: Up- and down-count are controlled by
When this field is set to "10" or "11", the setting value in
[ENxRATE] becomes 2-complementary.
The value in [ENxRATE] < 0 makes down-count, and
00 R/W
[ENxRATE] ≥ 0, up-count.
[Encoder mode, Sensor mode (Event count) and Phase
counter mode (Phase difference measurement)]
Auto judgment is done (refer to "3.3.2.1 Rotation Edge Detection
and Direction Signal Generation").
[Sensor mode (Timer count) and Timer mode]
Up-count is done.
Advanced Encoder Input Circuit(32-bit)
Description
[ENxRATE] register.
40 / 55
TXZ Family
Rev. 1.1