Phase Count; Figure 3.7 3-Phase Decode ([Enxtncr]<P3En>=1); Figure 3.8 2-Phase Decode ([Enxtncr]<P3En>=0) - Toshiba TXZ Series Reference Manual

3.2.2.3. Phase Count

(1) 3-phase decode ([ENxTNCR]<P3EN>=1)
[ENxRATE]<RATE>
Set clock
ENCxA(U)
ENCxB(V)
ENCxZ(W)
Rotation edge pulse ENCLK
Rotation direction
ENCxTIMPLS
(2-division)
Counter
Capture Register 0 (ini)
Interrupt INTENCx0
Reversed error REVERR
(2) 2-phase decode ([ENxTNCR]<P3EN>=0)
[ENxRATE]<RATE>
Set clock
ENCxA(U)
ENCxB(V)
ENCxZ(W)
Rotation edge pulse ENCLK
Rotation direction
ENCxTIMPLS
(2-division)
Counter
Capture register 0 (ini)
Interrupt INTENCx0
Reversed error REVERR
The hall sensor inputs (U, V, and W) are connected to ENCxA, ENCxB, and ENCxZ, respectively. When
<P3EN>=0, the frequency of 2-phase inputs (ENCxA and ENCxB) are multiplied by 4, and when <P3EN>=1, the
frequency of 3-phase inputs (ENCxA, ENCxB, and ENCxZ) are multiplied by 6. Then, the rotation edge pulses
(ENCLK) are generated.
Using <UDMD> setting and [ENxRATE] register setting, the up-count of the counter or the down-count is
controlled. The counter operates with any frequency. At up-count, when the counter value becomes
[ENxRELOAD] value, the counter is cleared to "0". At down-count, when the counter value becomes
2018-10-11
DIR
CW direction
1 2 3 0 1 2 3 0 1 2 3 0 1 2 3
3
Figure 3.7 3-phase decode ([ENxTNCR]<P3EN>=1)
DIR
CW direction
1 2 3 0 1 2 3 0 1 2 3 0 1 2 3
Figure 3.8 2-phase decode ([ENxTNCR]<P3EN>=0)
Advanced Encoder Input Circuit(32-bit)
2 3 0 1 2 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2
3
2 3 0 1 2 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2
3 3
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TXZ Family
CCW direction
2 3
CCW direction
2 3
Rev. 1.1