Enxintcr] (Interrupt Control Register) - Toshiba TXZ Series Reference Manual

4.2.12. [ENxINTCR] (Interrupt Control Register)

Bit Bit Symbol
31:6 -
5 MCMPIE
4 RLDIE
3 CMPIE
2 ERRIE
1 CAPIE
0 TPLSIE
2018-10-11
After Reset Type
0 R Read as "0".
MCMP met interrupt enable
0: Disable
0 R/W 1: Enable
When "1" is set to this bit and MCMP is met, INTENCx1 is
generated.
RELOAD match interrupt enable
0: Disable
1: Enable
0 R/W
When "1" is set to this bit and RELOAD matches, INTENCx1 is
generated.
In Encoder mode and Sensor mode (Event count), the interrupt is
not generated.
INT match interrupt enable
0: Disable
0 R/W 1: Enable
When "1" is set to this bit and INT matches, INTENCx1 is
generated.
Detection error interrupt enable
0: Disable
1: Enable
When "1" is set to this bit and the edge detection error ([ENxSTS]
0 R/W
<PDERR>) occurs or the skip detection ([ENxSTS]<SKPDT>) is
done, INTENCx0 is generated.
In Timer mode and Phase counter mode, the interrupt is not
generated.
Capture trigger interrupt enable
0: Disable
1: Enable
When "1" is set to this bit and the external trigger (ENCxZ input) or
0 R/W
the rotation edge pulse (ENCLK) captures the counter value,
INTENCx0 is generated.
In Encoder mode and Sensor mode (Event count), the interrupt is
not generated.
Rotation edge division interrupt enable
0: Disable
1: Enable
0 R/W
When "1" is set to this bit, INTENCx0 is generated by a rotation
edge division pulse.
In the other modes than Encoder mode and Sensor mode (Event
count), the interrupt is not generated.
Advanced Encoder Input Circuit(32-bit)
Description
51 / 55
TXZ Family
Rev. 1.1