Figure 3.2 Encxz Input Is Invalid ([Enxtncr]<Zen>=0) - Toshiba TXZ Series Reference Manual

(2) ENCxZ input is invalid ([ENxTNCR]<ZEN>=0).
In the case of [ENxRELOAD]=0x00000380 and [ENxINT]=0x00000002;
ENCxA
ENCxB
ENCxZ
Rotation edge pulse ENCLK
Internal Z-phase detection signal
Z-phase detection <ZDET>
Rotation direction
Count clear
ENCxTIMPLS
(2-division)
Counter
Interrupt INTENCx1
In the encoder mode, incremental encoder signals should be connected to ENCxA, ENCxB, and ENCxZ pins. The
frequencies of ENCxA and ENCxB signals are multiplied by 4. Then, the rotation edge pulses are counted.
When the rotation is done in CW direction (ENCxA is 90 degrees ahead comparing with ENCxB), the counter
value increments. After the counter value matches the value in [ENxRELOAD], the counter is cleared to "0" at the
next ENCLK.
When the rotation is done in CCW direction (ENCxA is 90 degrees late comparing with ENCxB), the counter
value decrements. After the counter value equals to "0x00000000", the counter value is set to the value in
[ENxRELOAD] at the next ENCLK.
When <ZEN> is set to "1", ENCxZ pin input is valid.
When <ZEN>=1 and <ZEACT>=0 (Input positive logic), the counter is cleared to "0" by the rising edge of
ENCxZ in the CW-direction rotation, and by the falling edge of ENCxZ in the CCW-direction rotation.
When <ZEN>=1 and <ZEACT>=1 (Input negative logic), the counter is cleared to "0" by the falling edge of
ENCxZ in the CW-direction rotation, and by the rising edge of ENCxZ in the CCW-direction rotation.
If ENCLK timing coincides with ENCxZ detection timing, the counter is cleared to "0" without counting.
When [ENxTNCR]<ENCLR> is set to "1", the counter is cleared to "0".
When the rotation direction is detected as CW, [ENxSTS]<UD> is set to "1", and detected as CCW, set to "0".
[ENxTNCR]<DECMD> can set the detecting direction to CW only or CCW only. And, when <DECMD> is not
"00", the rotation edge is detected by comparing the input state ([ENxINPMON]<DETMONA>, <DETMONB>,
and <DETMONZ>) stored at the previous edge detection with the current input values.
The signal dividing ENCLK (ENCxTIMPLS) is output.
2018-10-11
fsys
DIR
CW direction
110 111 112 113
Figure 3.2 ENCxZ input is invalid ([ENxTNCR]<ZEN>=0).
Advanced Encoder Input Circuit(32-bit)
0 1 2 0 1
13 / 55
CCW direction
0 380 37F 37E
TXZ Family
37D 37C
Rev. 1.1