Timer Mode; Figure 3.9 Encxz Input Is Valid ([Enxtncr]<Zen>=1); Figure 3.10 Encxz Input Is Invalid ([Enxtncr]<Zen>=0) - Toshiba TXZ Series Reference Manual

3.2.3. Timer Mode

This circuit can be used as a general purpose 32-bit timer.
●
32-bit up-counter (fsys clock for counting)
●
Counter clear control (Software clear, Comparison match clear, and External trigger)
●
A match interrupt is generated by the comparison function.
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Capture function: External trigger capture (an interrupt generation available), and Software capture
(1) ENCxZ input is valid ([ENxTNCR]<ZEN>=1).
[ENxINT]=0x00000006
ENCxZ
Internal Z-phase detection signal
Z-phase edge selection <ZESEL>
Count clear
ENCxTIMPLS
(2-division)
Counter
Capture register
Interrupt INTENCx0
Interrupt INTENCx1
(2) ENCxZ input is invalid ([ENxTNCR]<ZEN>=0).
[ENxINT]=0x00000006
ENCxZ
Internal Z-phase detection signal
Z-phase edge selection <ZESEL>
Count clear
Software capture
ENCxTIMPLS
(2-division)
Counter
Capture register
Interrupt INTENCx1
2018-10-11
fsys
10
2 3 4 5 6 7 8 9 A B 0 1 2 3 4
0 (ini)
Comparison interrupt
Figure 3.9 ENCxZ input is valid ([ENxTNCR]<ZEN>=1).
fsys
10
2 3 4 5 6 7 8 9 A B C D E F
0 (ini)
Comparison interrupt
Figure 3.10 ENCxZ input is invalid ([ENxTNCR]<ZEN>=0).
Advanced Encoder Input Circuit(32-bit)
31 32 33 34 35 36 37 38 39 40 41 0 1 2 3 4 5 6 7 8
B
Capture interrupt
10 31 32 33 34 35 36 0 1 2 3 4 5 6 7 8 9 A B C D
A A
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TXZ Family
01
B 41
Capture interrupt
Comparison interrupt
01
36
Comparison interrupt
Rev. 1.1