Toshiba TXZ Series Reference Manual page 24

TXZ Family
Advanced Encoder Input Circuit(32-bit)
When <ZEN>=1, ENCxZ input is used as an external trigger. When <ZEN>=0, no external triggers are used.
Using [ENxTNCR]<UDMD> setting and [ENxRATE] register setting, the up-count and the down-count of the
counter are controlled with any frequency clock.
At up-count, when the counter value becomes [ENxRELOAD] value, the counter is cleared to "0".
At down-count, when the counter value becomes "0x00000000", the counter value is set to [ENxRELOAD] value.
When [ENxTNCR]<TOVMD>=1 is set, the counter stops at the value in [ENxRELOAD].
When [ENxTNCR]<ENCLR> is set to "1", the counter is cleared to "0".
When <ZEN>=1 and [ENxTNCR]<ZESEL>=01, the counter is cleared to "0" by ENCxZ rising edge. And when
<ZESEL>=10, it cleared by ENCxZ falling edge, and, when <ZESEL>=11, cleared by both edges.
The counter value is captured by the edge detection of ENCxZ. The captured value can be read through
[ENxCNT] register.
When [ENxTNCR]<SFTCAP> is set to "1", the counter value is captured. The capture can be done at any timing.
The captured value can be read through [ENxCNT] register.
The value in [ENxCNT] register (the captured value) is kept regardless of the value of [ENxTNCR]<ENRUN>.
The capture value is cleared only by the reset.
When [ENxINTCR]<CMPIE>=1 and the counter value becomes [ENxINT] value, INTENCx1 interrupt can be
generated.
When [ENxINTCR]<MCMPIE>=1 and the counter value becomes [ENxMCMP] value, INTENCx1 interrupt can
be generated.
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2018-10-11 Rev. 1.1