[Cantsp](Time Stamp Counter Prescaler Register); [Cantsc](Time Stamp Counter Register) - Toshiba TXZ Series Reference Manual

[CANTSP](Time Stamp Counter Prescaler Register)

Bit Bit Symbol After Reset Type
31:4 - 0
3:0 TSP[3:0] 0
To ensure that the value of the [CANTSC] will not change during the write cycle to the mailbox, a hold register is
implemented. The value of the [CANTSC] will be copied to the hold register and then written to the mailbox from
the hold register if a message has been received or transmitted successfully. The reception is successful for the
receiver, if there is no error but the last one bit of End-of-frame. Transmission is successful for the transmitter if
there is no error until the last bit of End-of-frame. (Refer to the CAN specification 2.0B).

[CANTSC](Time Stamp Counter Register)

Bit Bit Symbol After Reset Type
31:16 - 0
15:0 TSC[15:0] 0
The overflow of the [CANTSC] can be detected by the time stamp counter overflow interrupt flag <TSOIF> of the
global interrupt flag register [CANGIF], and the time stamp counter overflow flag <TSO> of the global status
register [CANGSR]. Both flags can be cleared by writing "1" to <TSOIF> in the [CANGIF] register.
There is a 4-bit prescaler for the [CANTSC]. After power-up the time stamp counter is driven directly from the bit
clock ([CANTSP]<TSP[3:0]>=0). The period T
formula:
T = TBIT × ([CANTSP]<TSP[3:0]> + 1)
TSC
2018-10-30
R Read as "0".
Time stamp counter prescaler
R/W
Sets the value to be loaded to the prescaler for the 4-bit TSC.
R Read as "0".
Time stamp counter
R
Free running 16-bit counter
for the time stamp counter will be calculated by the following
TSC
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Function
Function
TXZ Family
CAN Controller
Rev. 1.1