[Cantrs](Transmission Request Set Register) - Toshiba TXZ Series Reference Manual

[CANTRS](Transmission Request Set Register)

Bit Bit Symbol After Reset Type
31 - 0
30:0 TRS[30:0] 0
Note: Mailbox 31 is receive only mailbox.
The transmission request set register can be set by a write of "1" from the CPU to only the [CANTRS]<TRSn>
bits of the mailboxes configured for transmission. The [CANTRS]<TRSn> bits of the mailboxes configured for
reception cannot be set.
The [CANTRS]<TRSn> bit is cleared to "0" when the message has been successfully transmitted or the
transmission request is reset by setting the [CANTRR]<TRRn> bit to "1".
When the transmission fails, the transmission process is repeated until it succeeds or the transmission request is
reset by setting the [CANTRR]<TRRn> bit to "1".
When the [CANTRS]<TRSn> bit is "1", do not write to mailbox n.
2018-10-30
R Read as "0"
Transmit request set (Each bit corresponds to mailboxes 30 to 0.)
Set <TRSn> requests the message transmission of corresponding mailbox n.
When the transmission is requested for multiple mailboxes, the message is transmitted in
R/W
accordance with the priority corresponding to the [CANMCR]<MTOS> bit.
A write of "1" from the CPU to mailbox x configured as transmission mailbox can set the bit. A
write of "0" from the CPU is invalid.
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Function
TXZ Family
CAN Controller
Rev. 1.1