[Canmbtif](Mailbox Transmit Interrupt Flag Register); [Canmbrif](Mailbox Receive Interrupt Flag Register); [Canmbim](Mailbox Interrupt Mask Register) - Toshiba TXZ Series Reference Manual

[CANMBTIF](Mailbox Transmit Interrupt Flag Register)

Bit Bit Symbol After Reset Type
31 - 0
30:0 MBTIF[30:0] 0
When the mailbox is set to receive, the corresponding bit in the [CANMBTIF] register is read as "0". When the
mailbox is set to transmit, the corresponding bit in the [CANMBRIF] register is read as "0".

[CANMBRIF](Mailbox Receive Interrupt Flag Register)

Bit Bit Symbol After Reset Type
31:0 MBRIF[31:0] 0

[CANMBIM](Mailbox Interrupt Mask Register)

Bit Bit Symbol After Reset Type
31:0 MBIM[31:0]
The settings in [CANMBIM] determine, for which mailbox the interrupt generation is enabled or disabled.
If a bit in [CANMBIM] is "0", the interrupt generation for the corresponding mailbox is disabled and if it is "1",
the interrupt generation is enabled. Reset value of [CANMBIM] is "0".
2018-10-30
R Read as "0".
Mailbox transmission interrupt flag (Each bit corresponds to mailboxes 30 to 0.)
When the message in mailbox n has been successfully transmitted and the interrupt
mask of the [CANMBIM] register is enabled (<MBIMn>=1), the <MBTIFn> bit is set to "1"
and the transmission completion interrupt (INTCANTXD) becomes the "High" level.
When [CANMBIM]<MBIMn> bit is "0", the <MBTIFn> bit is not set and INTCANTXD
R/W
stays at the "Low" level.
Transmission completion is checked by reading the [CANTA] register.
If even one bit in the [CANMBTIF] register is "1", INTCANTXD is the "High" level.
The <MBTIFn> bit is cleared by a write of "1" to the <MBTIFn> bit from the CPU.
A write of "0" is invalid.
Mailbox receive interrupt flag (Each bit corresponds to mailboxes 31 to 0.)
When mailbox n has successfully received the message and the interrupt mask of the
[CANMBIM] register is enabled (<MBIMn> = 1), the <MBRIFn> When the <MBIMn> bit in
the ,[CANMBIM] register is "0", the <MBRIFn> bit is not set and INTCANRXD stays at the
R/W
"Low" level. Receive completion is checked by reading the [CANRMP] register.
If even one bit in the [CANMBRIF] register is "1", INTCANRXD is the "High" level.
The <MBRIFn> bit is cleared by a write of "1" to the <MBRIFn> bit from the CPU.
A write of "0" is invalid.
Mailbox interrupt mask
0 R/W 0: Interrupt disabled for corresponding mailbox
1: Interrupt enabled for corresponding mailbox
Function
Function
Function
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TXZ Family
CAN Controller
Rev. 1.1