[Canta](Transmission Acknowledge Register); [Canaa](Abort Acknowledge Register) - Toshiba TXZ Series Reference Manual

32-bit risc microcontroller. can controller (can-a)
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[CANTA](Transmission Acknowledge Register)

Bit
Bit Symbol
After Reset Type
31
-
0
30:0
TA[30:0]
0
Note: Mailbox 31 is receive only mailbox
The [CANTA]<TAn> bit is set to "1" when a message in mailbox n has been successfully transmitted.
When the mailbox interrupt is enabled by setting the corresponding <MBIMn> bit in the mailbox interrupt mask
register [CANMBIM] to "1", the <MBTIFn> bit of the mailbox transmission interrupt flag register [CANMBTIF]
is set to "1" and the CAN transmission completion interrupt INTCANTXD occurs.
A write of "1" to the <TAn> bit or the [CANTRS]<TRSn> bit from the CPU can clear the <TAn> bit. A write of
"0" to the <TAn> bit or the [CANTRS]<TRSn> bit from the CPU is invalid.

[CANAA](Abort Acknowledge Register)

Bit
Bit Symbol
After Reset Type
31
-
0
30:0
AA[30:0]
0
Note: Mailbox 31 is receive only mailbox.
The [CANAA]<AAn> bit is set to "1" when a message in mailbox n has not been successfully transmitted.
When [CANGIF]<TRMABF> bit in the global interrupt flag register is also set to "1", and the transmission abort
interrupt is enabled by setting the [CANGIM]<TRAMABM> bit in the global interrupt mask register to "1", the
CAN global interrupt(INTCANGLB) occurs.
A write of "1" to the <AAn> bit or the [CANTRS]<TRSn> bit from the CPU can clear the <AAn> bit. A write of
"0" to the <AAn> bit or the [CANTRS]<TRSn> bit from the CPU is invalid.
2018-10-30
R
Read as "0".
Transmission acknowledge (Each bit corresponds to mailboxes 30 to 0)
When the message in mailbox n has been successfully transmitted, the <TAn> bit is set to "1".
R/W
The <TAn> bit can be cleared by a write of "1" from the CPU to the <TAn> bit or the
[CANTRS]<TRSn> bit.
R
Read as "0".
Abort acknowledge (Each bit corresponds to mailboxes 30 to 0.)
When the message in mailbox n has not been successfully transmitted, the <AAn> bit is set to
R/W
"1".
The <AAn> bit can be cleared by a write of "1" from CPU to the <AAn> bit or the
[CANTRS]<TRSn> bit.
36 / 54
Function
Function
TXZ Family
CAN Controller
Rev. 1.1

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