Param0: System Pll Input Frequency And Param1: Expected System Clock; Param2: Mode; Reserved - NXP Semiconductors LPC1311 User Manual

NXP Semiconductors
The routine returns a result code that indicates if the system PLL was successfully set
(PLL_CMD_SUCCESS) or not (in which case the result code identifies what went wrong).
The current system frequency value is also returned. The application should use this
information to adjust other clocks in the device (the SSP, UART, and WDT clocks, and/or
clockout).
Table 64.
Routine
Input
Result
The following definitions are needed when making set_pll power routine calls:
/* set_pll mode options */
#define
#define
#define
#define
/* set_pll result0 options */
#define
#define
#define
#define
#define
For a simplified clock configuration scheme see

5.5.1.1 Param0: system PLL input frequency and Param1: expected system clock

set_pll looks for a setup in which the system PLL clock does not exceed 72 MHz. It easily
finds a solution when the ratio between the expected system clock and the system PLL
input frequency is an integer value, but it can also find solutions in other cases.
The system PLL input frequency (Param0) must be between 10000 to 25000 kHz (10
MHz to 25 MHz) inclusive. The expected system clock (Param1) must be between 1 and
72000 kHz inclusive. If either of these requirements is not met, set_pll returns
PLL_INVALID_FREQ and returns Param0 as Result1 since the PLL setting is unchanged.

5.5.1.2 Param2: mode

The first priority of set_pll is to find a setup that generates the system clock at exactly the
rate specified in Param1. If it is unlikely that an exact match can be found, input parameter
mode (Param2) should be used to specify if the actual system clock can be less than or
equal, greater than or equal or approximately the value specified as the expected system
clock (Param1).
A call specifying CPU_FREQ_EQU will only succeed if the PLL can output exactly the
frequency requested in Param1.
UM10375
User manual
set_pll routine
set_pll
Param0: system PLL input frequency (in kHz)
Param1: expected system clock (in kHz)
Param2: mode (CPU_FREQ_EQU, CPU_FREQ_LTE, CPU_FREQ_GTE,
CPU_FREQ_APPROX)
Param3: system PLL lock time-out
Result0: PLL_CMD_SUCCESS | PLL_INVALID_FREQ | PLL_INVALID_MODE |
PLL_FREQ_NOT_FOUND | PLL_NOT_LOCKED
Result1: system clock (in kHz)
CPU_FREQ_EQU 0
CPU_FREQ_LTE 1
CPU_FREQ_GTE 2
CPU_FREQ_APPROX 3
PLL_CMD_SUCCESS 0
PLL_INVALID_FREQ 1
PLL_INVALID_MODE 2
PLL_FREQ_NOT_FOUND 3
PLL_NOT_LOCKED 4
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 14 June 2011
UM10375
Chapter 5: LPC13xx Power profiles
Figure 7. For more details see
© NXP B.V. 2011. All rights reserved.
Figure 3.
56 of 368