NXP Semiconductors PN7150 Hardware Design Manual page 9

NXP Semiconductors
For VEN lower than 0.4V the PN7150 is in hard power down state and the chip's internal
core is no more supplied.
The chip is reset when VEN is switched back to a voltage level higher than 1.1V.
It is strongly recommended to foresee a control of VEN pin from the host controller side
so that it can reset PN7150 whenever needed.
The VEN pad state is considered as valid information only when the VDD(PAD) pad is
supplied.
Indeed, VEN signal is supposed to be driven by the host controller with which VDD(PAD)
supply is shared. When the supply is not there, this means that the host controller is not
able to drive a meaningful state on the PN7150 VEN pin.
An internal pull-down resistor can be programmed on the PN7150 internal VEN signal in
order to define a clear pin state when it is not externally driven by the host (details can be
found in PN7150 User Manual [2]). It means that when the device is powered-up with
VBAT and VDD(PAD) supplied to the PN7150, the NFC chip will stand in hard power
down until the host controller explicitly drives the VEN pin to the digital high state (during
its boot sequence).
The full PN7150 power states, considering VBAT, VDD(PAD) and VEN pin level, is given
in PN7150 Product datasheet [1].
AN11756
Application note
COMPANY PUBLIC
All information provided in this document is subject to legal disclaimers.
Rev. 1.2 — 15 January 2018
347612
AN11756
PN7150 Hardware Design Guide
© NXP B.V. 2018. All rights reserved.
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