Contents - NXP Semiconductors PN7150 Hardware Design Manual

NXP Semiconductors

16. Contents

1. Introduction ......................................................... 3
2. Interfaces ............................................................. 4
3. Typical application schematics .......................... 6
4. Host interface ...................................................... 7
4.1 Host interface pinning ........................................ 7
4.2 Host interface pin characteristics ....................... 7
4.3 Digital interface levels ........................................ 7
4.4 I²C bus specificities ............................................ 7
4.5 Frames reading synchronization ........................ 8
4.6 Reset control (VEN) ........................................... 8
5. Clock interface ................................................... 10
5.1 Use of crystal oscillator .................................... 10
5.2 Use of system clock ......................................... 11
5.2.1 Input clock characteristics ................................ 11
5.2.2 Clock request mechanism ................................ 11
6. Power interface .................................................. 13
6.1 Power Management Unit .................................. 13
6.2 External capacitors requirement ....................... 13
6.3 Power application schematic ............................ 13
6.4 TVDD supply options ....................................... 14
6.4.1 Config 1: VBAT used to generate TVDD .......... 14
6.4.2 Config 2: external 5V used to generate TVDD . 16
6.4.3 TVDD configuration summary .......................... 16
7. Antenna interface .............................................. 18
7.1 Typical matching circuit .................................... 18
7.2 Matching circuit BoM optimization .................... 18
7.2.1 Damping resistors ............................................ 19
7.2.2 C parallel capacitor ......................................... 19
2
7.2.3 Rx path ............................................................. 20
8. Power modes ..................................................... 21
9. Layout guidelines .............................................. 22
9.1 Antenna EMC inductors ................................... 22
9.2 RF paths........................................................... 23
9.3 XTAL layout recommendations ........................ 25
9.4 Input clock ........................................................ 25
9.5 De-Coupling (blocking) capacitors ................... 25
10. Q&A .................................................................... 26
11. References ......................................................... 27
12. Abbreviations .................................................... 28
13. Legal information .............................................. 29
13.1 Definitions ........................................................ 29
13.2 Disclaimers....................................................... 29
13.3 Licenses ........................................................... 29
13.4 Trademarks ...................................................... 29
PN7150 Hardware Design Guide
14. List of figures ..................................................... 30
15. List of tables ...................................................... 31
16. Contents ............................................................. 32
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in the section 'Legal information'.
© NXP B.V. 2018.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
AN11756
All rights reserved.
Date of release: 15 January 2018
347612
Document identifier: AN11756