Clock Dividers; Cpu Clock Configuration Register (Cclkcfg - 0X400F C104) - NXP Semiconductors LPC1768 User Manual

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7. Clock dividers

The output of the PLL0 must be divided down for use by the CPU and the USB subsystem
(if used with PLL0, see
frequency can be determined independently from the USB subsystem, which always
requires 48 MHz with a 50% duty cycle for proper operation.
osc_clk
sysclk
Fig 10. PLLs and clock dividers

7.1 CPU Clock Configuration register (CCLKCFG - 0x400F C104)

The CCLKCFG register controls the division of the PLL0 output before it is used by the
CPU. When PLL0 is bypassed, the division may be by 1. When PLL0 is running, the
output must be divided in order to bring the CPU clock frequency (CCLK) within operating
limits. An 8-bit divider allows a range of options, including slowing CPU operation to a low
rate for temporary power savings without turning off PLL0.
Note: when the USB interface is used in an application, CCLK must be at least 18 MHz in
order to support internal operations of the USB subsystem.
Table 37.
Bit Symbol
7:0 CCLKSEL
The CCLK is derived from the PLL0 output signal, divided by CCLKSEL + 1. Having
CCLKSEL = 1 results in CCLK being one half the PLL0 output, CCLKSEL = 3 results in
CCLK being one quarter of the PLL0 output, etc.
UM10360_0
User manual
Section 4–6). Separate dividers are provided such that the CPU
USB PLL settings
(PLL1...)
USB PLL
(PL160M)
main PLL
CPU PLL
settings
select
(PLL0...)
(PLL0CON)
Main PLL
(PL550M) pllclk
CPU Clock Configuration register (CCLKCFG - address 0x400F C104) bit
description
Value Description
Selects the divide value for creating the CPU clock (CCLK) from
the PLL0 output.
0 to 1 Not allowed, the CPU clock will always be greater than 100 MHz.
2 PLL0 output is divided by 3 to produce the CPU clock.
3 PLL0 output is divided by 4 to produce the CPU clock.
4 PLL0 output is divided by 5 to produce the CPU clock.
: :
255 PLL0 output is divided by 256 to produce the CPU clock.
Rev. 00.06 — 5 June 2009
Chapter 4: LPC17xx Clocking and power control
USB PLL select
(PLL1CON)
usb_clk
USB
Clock
Divider
USB clock divider setting
USBCLKCFG[3:0]
CPU
Clock
Divider
CPU clock divider setting
CCLKCFG[7:0]
UM10360
cclk
Reset
value
0x00
© NXP B.V. 2009. All rights reserved.
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