Fig 20. Xtal Connection Example; Xtal Layout Recommendations; Input Clock; De-Coupling (Blocking) Capacitors - NXP Semiconductors PN7150 Hardware Design Manual

NXP Semiconductors

9.3 XTAL layout recommendations

The XTAL must be connected as close as possible to the CLK1 and CLK2 pins from the
PN7150 to achieve the best performances as possible.
Please follow these guidelines for the layout of the XTAL connections:

Fig 20. XTAL connection example

9.4 Input clock

Clock signal must be:
• Shielded from the rest of the board
• Kept as short as possible

9.5 De-Coupling (blocking) capacitors

Standard layout rules consisting in decoupling capacitors being placed as close as
possible to the chip apply.
AN11756
Application note
COMPANY PUBLIC
- As the XTAL is very sensitive to parasitic capacitance and noise, we advise to:
put the XTAL far from other signals (especially other CLK lines or signals
o
with frequent switching)
limit the crosstalk between CLK lines and other signals
o
- Load capacitor connections:
Choose capacitor with a good temperature stability like COG
o
Place the capacitors closed to each other and close to the XTAL
o
Avoid to connect them to a dirty ground (perturbed by return current from
o
others functionalities on the board like USB, PWM or power supply lines)
All information provided in this document is subject to legal disclaimers.
Rev. 1.2 — 15 January 2018
347612
AN11756
PN7150 Hardware Design Guide
© NXP B.V. 2018. All rights reserved.
25 of 32