Low Power Bit Usage; Mcg Internal Reference Clocks; External Reference Clock - NXP Semiconductors MK30DX64VMC7 Reference Manual

K30 sub-family

Table of Contents

Chapter 24 Multipurpose Clock Generator (MCG)

the FLL remains unlocked for several reference cycles. DCO startup time is equal to the

FLL acquisition time. After the selected DCO startup time is over, the FLL is locked. The

completion of the switch is shown by the C4[DRST_DRS] read bits.

24.4.2 Low Power Bit Usage

The C2[LP] bit is provided to allow the FLL or PLL to be disabled and thus conserve

power when these systems are not being used. The C4[DRST_DRS] can not be written

while C2[LP] bit is 1. However, in some applications, it may be desirable to enable the

FLL or PLL and allow it to lock for maximum accuracy before switching to an engaged

mode. Do this by writing C2[LP] to 0.

This module supports two internal reference clocks with nominal frequencies of 32 kHz

(slow IRC) and 4 MHz (fast IRC). The fast IRC frequency can be divided down by

programming of the FCRDIV to produce a frequency range of 32 kHz to 4 MHz.

24.4.3.1 MCG Internal Reference Clock

The MCG Internal Reference Clock (MCGIRCLK) provides a clock source for other on-

chip peripherals and is enabled when C1[IRCLKEN]=1. When enabled, MCGIRCLK is

driven by either the fast internal reference clock (4 MHz IRC which can be divided down

by the FRDIV factors) or the slow internal reference clock (32 kHz IRC). The IRCS

clock frequency can be re-targeted by trimming the period of its IRCS selected internal

reference clock. This can be done by writing a new trim value to the

C3[SCTRIM]:C4[SCFTRIM] bits when the slow IRC clock is selected or by writing a

new trim value to the C4[FCTRIM] bits when the fast IRC clock is selected. The internal

reference clock period is proportional to the trim value written.

C3[SCTRIM]:C4[SCFTRIM] (if C2[IRCS]=0) and C4[FCTRIM] (if C2[IRCS]=1) bits

affect the MCGOUTCLK frequency if the MCG is in FBI or BLPI modes.

C3[SCTRIM]:C4[SCFTRIM] (if C2[IRCS]=0) bits also affect the MCGOUTCLK

frequency if the MCG is in FEI mode.

Additionally, this clock can be enabled in Stop mode by setting C1[IRCLKEN] and

C1[IREFSTEN], otherwise this clock is disabled in Stop mode.

K30 Sub-Family Reference Manual, Rev. 1.1, Dec 2012

Freescale Semiconductor, Inc.