Samsung S3C84I8 User Manual page 287

S3C84I8/F84I8/84I9/F84I9
MSB
Operating mode and
baud rate selection bits
(see table below)
Multiprocessor communication
enable bit (mode 2 only):
0 = Disable
1 = Enable
Serial data receive enable bit:
0 = Disable
1 = Enable
If parity disable mode (PEN = 0),
location of the 9th data bit to be transmitted in
UART mode 2 ("0" or "1").
If parity enable mode (PEN = 1),
Even/odd parity selection bit for transmit data in
UART mode 2;
0 : Even parity bit generation for transmit data
1 : Odd parity bit generation for transmit data
NOTES:
1. In mode 2, if the UARTCON.5 bit is set to "1" then the receive interrupt will not be
activated if the received 9th data bit is "0". In mode 1, if UARTCON.5 = "1" then the
receive interrut will not be activated if a valid stop bit was not received.
2. The descriptions for 8-bit and 9-bit UART mode do not include start and stop bits
for serial data receive and transmit.
3. Parity enable bits, PEN, is located in the UARTPND register at address F4H.
4. Parity enable and parity error check can be available in 9-bit UART mode
(Mode 2) only.
UART Control Register (UARTCON)
F6H, Set1, Bank 0, R/W, Reset Value: 00H
MS1 MS0 MCE RE
(1)
(2)
MS1 MS0 Mode Description
0 0 0 Shift register
0 1 1 8-bit UART
1 x 2 9-bit UART
Figure 15-1. UART Control Register (UARTCON)
TB8 RB8 RIE
TIE
Transmit interrupt enable bit:
0 = Disable
1 = Enable
Received interrupt enable bit:
0 = Disable
1 = Enable
If parity disable mode (PEN = 0),
location of the 9th data bit that was received in
UART mode 2 ("0" or "1").
If parity enable mode (PEN = 1),
Even/odd parity selection bit for receive data in
UART mode 2.
0 : Even parity check for the received data
1 : Odd parity check for the received data
Baud Rate
fxx / (16 x (16bit BRDATA + 1))
fxx / (16 x (16bit BRDATA + 1))
fxx / (16 x (16bit BRDATA + 1))
LSB
UART
15-3