Samsung S3C84I8 User Manual page 225

CLOCK CIRCUIT
CLOCK STATUS DURING POWER-DOWN MODES
The two power-down modes, Stop mode and Idle mode, affect the system clock as follows:
— In Stop mode, the main oscillator is halted. Stop mode is released, and the oscillator is started, by a reset
operation or an external interrupt (with RC delay noise filter). ), and can be released by internal interrupt too
when the sub-system oscillator is running and watch timer is operating with sub-system clock.
— In Idle mode, the internal clock signal is gated to the CPU, but not to interrupt structure, timers and timer/
counters. Idle mode is released by a reset or by an external or internal interrupt.
INT
Main-Ststem
Oscillator
Circuit
Stop
OSCCON.3
OSCCON.0
STOP OSC
inst.
STPCON
CLKCON.4-.3
7-2
Stop Release
f
X
Selector 1
f
XX
1/8-1/4096
Frequency
Dividing
Circuit
1/1 1/2 1/8
Selector 2
Figure 7-3. System Clock Circuit Diagram
Sub-system
f
XT
Oscillator
Circuit
Basic Timer
Timer/Counter
Watch Timer (fxx/256)
UART
A/D Converter
1/16
System Clock
IDLE Instruction
S3C84I8/F84I8/C84I9/F84I9
Watch Timer
Stop
OSCCON.2
CPU Clock