Samsung S3C84I8 User Manual page 123

S3C84I8/F84I8/C84I9/F84I9
Levels
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
NOTES:
1. Within a given interrupt level, the lower vector address has high priority. For example, DCH has
higher priority than DEH within the level IRQ5 the priorities within each level are set at the factory.
2. External interrupts are triggered by a rising or falling edge, depending on the corresponding control
register setting.
Vectors
BEH
C0H
C2H
C4H
C6H
C8H
CAH
CEH
D0H
D2H
D4H
D6H
D8H
DAH
DCH
DEH
Figure 5-2. S3C84I8/F84I8/C84I9/F84I9Interrupt Structure
Sources
Timer B underflow
Timer A match/capture
Timer A overflow
Timer 1(0) match/capture
Timer 1(0) overflow
Timer 1(1) match/capture
Timer 1(1) overflow
P1.0 external interrupt
P1.1 external interrupt
P1.2 external interrupt
P1.3 external interrupt
Watch timer
SIO receive/transmit
PWM overflow interrupt
UART data receive
UART data transmit
INTERRUPT STRUCTURE
Reset(Clear)
H/W
H/W, S/W
H/W, S/W
H/W, S/W
H/W, S/W
H/W, S/W
H/W, S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
5-5