Samsung S3C84I8 User Manual page 268

16-BIT TIMER 1(0,1)
MSB
Timer 1 clock source selection bit:
000 = fxx/1024
001 = fxx/256
010 = fxx/64
011 = fxx/8
100 = fxx
101 = External clock falling edge
110 = External clock rising edge
111 = Counter stop
Timer 1 operating mode selection bit:
00 = Interval mode
01 = Capture mode (capture on rising edge, OVF can occur)
10 = Capture mode (capture on falling edge, OVF can occur)
11 = PWM mode
NOTE: Interrupt pending bits are located in TINTPND register.
12-4
Timer 1 Control Register
(T1CON0) E8H, Set 1, Bank 1, R/W
(T1CON1) E9H, Set 1, Bank 1, R/W
.7 .6 .5
Figure 12-1. Timer 1(0,1) Control Register (T1CON0, T1CON1)
.4 .3 .2 .1
Timer 1 overflow interrupt enable bit
0 = Disable overflow interrupt
1 = Enable overflow interrrupt
Timer 1 match/capture interrupt enable bit:
0 = Disable interrupt
1 = Enable interrrupt
Timer 1 counter clear bit:
0 = No effect
1 = Clear counter (Auto-clear bit)
S3C84I8/F84I8/84I9/F84I9
.0 LSB