Samsung S3C84I8 User Manual page 134

INTERRUPT STRUCTURE S3C84I8/F84I8/C84I9/F84I9
INTERRUPT PENDING FUNCTION TYPES
Overview
There are two types of interrupt pending bits: one type that is automatically cleared by hardware after the interrupt
service routine is acknowledged and executed; the other that must be cleared in the interrupt service routine.
Pending Bits Cleared Automatically by Hardware
For interrupt pending bits that are cleared automatically by hardware, interrupt logic sets the corresponding
pending bit to "1" when a request occurs. It then issues an IRQ pulse to inform the CPU that an interrupt is waiting
to be serviced. The CPU acknowledges the interrupt source by sending an IACK, executes the service routine,
and clears the pending bit to "0". This type of pending bit is not mapped and cannot, therefore, be read or written
by application software.
In the S3C84I8/F84I8/C84I9/F84I9 interrupt structure, the timer B underflow interrupt (IRQ0) belongs to this
category of interrupts in which pending condition is cleared automatically by hardware.
Pending Bits Cleared by the Service Routine
The second type of pending bit is the one that should be cleared by program software. The service routine must
clear the appropriate pending bit before a return-from-interrupt subroutine (IRET) occurs. To do this, a "0" must be
written to the corresponding pending bit location in the source's mode or control register.
In the S3C84I8/F84I8/C84I9/F84I9 interrupt structure, pending conditions for IRQ3, IRQ4, IRQ5, IRQ6, and IRQ7
must be cleared in the interrupt service routine.
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