Power Failure; External Signal No; Interval Timer; Selector Channel No - RCA 70/46 Reference Manual

Priority No. Condition
1
Power Failure
2
Machine Check
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3 External Signal No. 1
4
External Signal" No.2
5 External Signal No. 3
6 External Signal No. 4
7 External Signal No. 5
8
External Signal No. 6
9 Interval Timer
10 Selector Channel No. 1
11 Selector Channel No. 2
12 Selector Channel No.3
13 Selector Channel No.
4
16 Multiplexor Channel
17 Elapsed Time Clock
Flag Bit
2 0
21
22
2
a
24
25
2
6
27
2 8
2
9
2 10
211
212
2
1 ;)
2
16
Table 9. Interrupt Conditions
Explanation
A power failure interrupt occurs when there is a power failure in the processor or
main memory caused by a line failure or by pressing the MASTER pushbutton indi-
cator on the 70/97 Console. Any instruction being executed at the time of interrupt
is terminated. It is a program restriction that the mask bit in processor state P
4
for
this interrupt condition must always be zero when this interrupt occurs. This permits
the program to operate in processor state P 4 for the purpose of closing down the
machine during a one-millisecond interval between power failure and actual power
loss to the system.
The machine check interrupt occurs when a machine fault or malfunction is detected.
Any instruction being executed at the time of interrupt is terminated. It is a pro-
gram restriction that the mask bit in processor state P 4 for this interrupt condition
must always be zero when this interrupt occurs. The following conditions can cause
a machine check interrupt to occur:
Scratch-Pad Memory Parity Error-This error can occur when data is read
from the Scratch-Pad Memory.
Main Memory or Non-Addressable Main Memory Parity Error-If a main
memory parity error occurs during an I/O data transfer, this interrupt condition does
not occur. A channel interrupt occurs and the program is notified of the condition via
the channel status byte.
The external signal interrupt occurs when a signal is received on an external line
(1-6) associated with the Direct Control option. Any instruction being executed at
the time of interrupt goes to completion.
Lapse of Interval Timer. This interrupt occurs at completion of an instruction.
This interrupt provides the means by which the processor can receive and act upon
signals from input/output devices connected to a Selector Channel (1-6) or the
Multiplexor Channel. This interrupt can occur as a result of the termination (normal
or abnormal) of an input/output operation or at the request of an input/output
device. It can also occur as the result of a program controlled interrupt. Any
instruction being executed at the time of interrupt goes to completion. (Selector
Channels are optional.)
This interrupt occurs when the Elapsed Time Clock counts downward from positive
to negative, indicating that its maximum range has been reached. Any instruction
being executed at the time of interrupt goes to completion. (The Elapsed Time Clock
is an option.)
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