Interrupt Mask Registers; Program Mask Registers - RCA 70/46 Reference Manual

Interrupt Status Registers
(Cont'd)
Interrupt Mask Registers
Program Mask Registers
Program Interrupt
2. When T
=
1, the D-bit within the virtual addresses (supplied by the
NIA field of the P counter or the effective operand addresses after
staticizing - except I/O instructions) specify either address trans-
lation or direct addressing.
D
=
1: Direct addressing.
D
=
0: Translate addressing.
Bit Position 14, the B-bit, is controlled by the hardware via the Func-
tion Call instruction to control which ROM bank is used. It has no
meaning to the software.
Bit Positi'on
15
is the non-privileged mode bit. This field is set by the
program to indicate the privileged status of the processor state being
initiated. If N
=
0, the initiated processor state runs in the privileged
mode, allowing execution of the privileged instructions; if N
=
1, the
processor state runs in the non-privileged mode, inhibiting the execution
of the privileged instructions.
Bit Positions
16
through
23
are not used and must be zeros.
Bit Positions 24 through
31
is the call field. This field is set during the
execution of a Supervisor Call instruction. The Rl and
R2
field of this
instruction provide a code which is placed into the call field of the Inter-
rupt Status register of the processor state in which the Supervisor Call
instruction is issued. This code provides linkage to the program required
to accomplish the purpose of the Supervisor Call instruction.
• The Interrupt Mask register is a 32-bit register. A separate register
is provided for each of the four processor states. Each bit in the Interrupt
Mask register is associated with an interrupt condition. A 0 bit in any bit
position in this register inhibits the associated interrupt condition; a 1 bit
in any bit position in this register permits the associated interrupt
condition.
Important:
1. The Power Failure and Machine Check interrupts must be inhibited
in the Machine Condition State P
4'
The mask bits in the Interrupt
Mask register for these interrupt conditions must always be zero.
This is a program restriction.
2. All interrupts except the Machine Check interrupt must be inhibited
in the Interrupt Control State p;{. The mask bit in the Interrupt
Mask register for this interrupt condition must always be zero.
This is a programming restriction .
• In addition to the Interrupt Mask register, a Program Mask register
is also provided for each state. The Program Mask register is not contained
in main memory or scratch-pad memory. It is a separate machine register
which is set by the non-privileged instruction, Set Program Mask, and it
applies to the following interrupt conditions:
20
Significance error.
Exponent underft.ow.
Decimal overft.ow.
Fixed-point overft.ow.