RCA 70/46 Reference Manual page 129

PROCESSOR
STATE CONTROL
INSTRUCTIONS
INTRODUCTION
INSTRUCTION
FORMAT
RR Format
Description
CONDITION CODE
UTILIZATION
INTERRUPT ACTION
• There are two control instructions that can be used in the Processing
State (P
J ) .
These instructions are Supervisor Call, and Set Program Mask.
These instructions can also be executed in any other state.
The Supervisor Call instruction enables the program to switch from
any state to the Interrupt Control State (P
a ).
Through this operation a
program in any processor state can communicate with and initiate the
I nterrupt Control State (P
a)
programs.
The Set Program Mask instruction permits the user to specify whether
or not the program is to be interrupted for any of the following errors:
1. significance error.
2. exponent underflow.
3. decimal overflow.
4. fixed-point overflow.
The execution of the Set Program Mask instruction causes the condition
code and program mask bits in the P counter of the state in which the
system is operating to be set to the value specified by the instruction. This
instruction always changes the condition code.
OpC~e ~ ~
o
7 8 11 12 15
• The RR format is used for the Supervisor Call and Set Program Mask
instructions. For the Set Program Mask instruction, the R2 field is ignored.
The contents of the general register specified by the Rl field form the
first operand.
For the Supervisor Call instruction, the Rl and R2 fields are combined
to become an immediate operand. This operand does not refer to any regis-
ter, but is a value which is placed in the Interrupt Status Register (ISR)
of the initiated state to provide communication with the software in
this state.
• The condition code is changed by the Set Program Mask instruction. The
condition code and program mask bits of the current P counter are replaced
by the contents of the general register (bits 2-7) specified by the first
address of the instruction.
• No error interrupts can occur as a result of using the instructions in
this section. The Supervisor Call instruction causes an interrupt, but this
interrupt is the desired result of its execution.
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