RCA 70/46 Reference Manual page 197

Notes
(Cont'd)
Logical
Instructions
3. The address is loaded into the rightmost 24 bits of General Register
1 (13 or 9). The leftmost eight bits are unaltered.
4. When a single instruction is used to edit multiple fields, the address
of the first significant digit of each field is loaded into the register.
However, only the address of the last field processed will be available
upon completion of the instruction.
5. In processor states PI and P
2,
General Register 1 is used. In processor
state P
3,
General Register 13 is used. In processor state P
4,
General
Register 9 is used.
6. In testing for Paging Error or Paging Queue interrupt conditions,
the hardware assumes that the number of bytes in the source field
is equal to the number of bytes in the pattern field. If the assumed
source field extends across two pages, of which the second page has
any of the conditions causing Paging Error or Paging Queue inter-
rupts, but the actual source field number of bytes is short enough
to fit within the first page, a false Paging Error condition or Paging
Queue Interrupt condition occurs.
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