RCA 70/46 Reference Manual page 135

INTERRUPT ACTION
Address Error
Addressing
Specification
Fixed-Point
Instructions
• The following interrupt conditions can occur as a result of fixed-point
instructions:
• An address error interrupt occurs when an address specifies a location
outside the available main memory. The operation is terminated at the
point of error. The result data and the condition code, if produced, are
unpredictable.
• An address error interrupt occurs when an instruction specifies a:
1. Full-word operand that is not located on a 32-bit boundary.
2. Halfword operand that is not located on a I6-bit boundary.
3. Double-word operand that is not located on a 64-bit boundary.
4. Register with an odd-numbered address when using an even/odd
pair containing a 64-bit operand.
The instruction is suppressed. The condition code, data in main memory,
and registers remain unchanged.
Protection • An address error interrupt occurs when the storage key and the protec-
tion key of the result location do not match. The operation is suppressed
and the condition code and data in the registers and main memory are
unaltered. The only exception is the Store Multiple instruction which is
terminated. The amount of data stored is unpredictable. (This interrupt
can only occur if the memory protect feature is installed.)
Data Error •
A data error interrupt occurs when an invalid digit or sign code of the
decimal operand is encount.ered in the Convert to Binary instruction. The
operation is suppressed and the condition code and data in the register and
main memory are unaltered.
Fixed-Point Overflow •
A fixed-point overflow interrupt occurs when the results overflow in
sign control, add, subtract or shift operations. The operation is completed
by placing the truncated result in the register and setting Condition Code 3.
Overflow bits are lost. If the fixed point program mask bit is reset, inter-
rupt will not occur and the flag in the IFR will not be set.
Divide Error •
A divide error interrupt occurs when the quotient would exceed the
register size in division, or the result of a Convert to Binary instruction
exceeds 31 bits. The operation is suppressed and the data in the registers
remains unaltered.
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