Rca Model 70/46 Processor - RCA 70/46 Reference Manual

INTRODUCTION
RCA MODEL 70/46
PROCESSOR
Compatibility
• The 70/46 Processor incorporates features which increase the efficiency
of the system for time-sharing use and for conventional batch processing.
This is accomplished by using main and subsidiary memory to create a
virtual memory of two million bytes. The virtual memory consists of
blocks of either 4,096 or 2,048 bytes which are called pages. An address
translation feature translates the addresses of the virtual memory pages
into actual addresses as assigned in working memory by the operating
system. The translated actual addresses are then stored in a translation
memory which is used to implement the virtual memory.
The 70/46 Processor is a halfword-organized, variable-format processor
consisting of main memory, nonaddressable main memory, scratch-pad
memory, translation memory, read-only memory, program control and
arithmetic unit, input/output control, and a program interval timer.
The 70/46 provides multiprogramming with multiaccess time-sharing
capabilities.
User programs may run interactively at remote terminals or sequen-
tially under the automatic control of a job stream monitor where the
presence of the user is not required. The 70/46 also features an efficient
technique for the handling of I/O data transfer through the reduction in
processing interference during I/O selector channel operations, and an
increase in the I/O transfer rate capability.
The Time Sharing Operating System, which is used with the 70/46
Processor, consists of a set of control routines, language processors, and
service routines which enable the complete system to provide efficient
batch processing concurrently with time-sharing operations from remote
terminals.
• All instructions, character codes, interrupt facilities, formats, and pro-
gramming features are functionally the same as corresponding features
on the 70/35, 70/45, and 70/55 Processors. Programs can be interchanged
between processors provided that:
1. Systems features are equivalent (Emulator features are not pro-
vided) .
2. Programs are written to be independent of strict timing considera-
tions.
3. Programs are restricted to specified functions and do not use unspeci-
fied characteristics peculiar to the hardware of either processor.
4. Program interrupts does not occur where an instruction is terminated
with unpredictable results.
5. Programs are written subject to all specified compatibility restric-
tions.
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