General Registers; Floating-Point Registers; Interrupt Status Registers - RCA 70/46 Reference Manual

Program Counter
(Cont'd)
General Registers
Floating-Point Registers
Interrupt Status Registers
Program Interrupt
Bit Positions 2 and 3 contain the condition code. When an interrupt
occurs or a Program Control instruction is executed, the condition code
is moved from a machine register, where it is maintained for instruction
execution, and stored in this field of the P counter of the state being ter-
minated. The condition code in this field of the P counter of the state being
initiated is moved into a machine register where it is maintained for
possible future use.
Bit Positions 4- through 7 contain the program mask. When an inter-
rupt occurs or a Program Control instruction is executed, the program
mask is moved from the machine register, where it is maintained for
instruction execution, and stored in bits 4 through 7 of the P counter of
the state being terminated. The program mask in this field of the P counter
of the state being initiated is moved into the machine register where it is
maintained for possible future use.
Bit Positions 8 through
31
contain the next instruction address. This
field stores the address of the next instruction in main memory to be
staticized by the appropriate processor state. Each time an instruction is
staticized, the P counter is updated to the next instruction. This field is
left intact whenever an interrupt requires switching to a new processor
state.
• A separate set of general registers is assigned to each processor state.
Each general register is 32 bits long. Sixteen general registers are assigned
to PI and P
2,
six general registers are assigned to P
3,
and five general
registers are assigned to P
4.
These registers serve as operands, base address
registers, or index registers .
• Four floating-point registers are provided. Each floating-point register
is 64 bits long (double length). These registers are used only in floating-
point arithmetic. The floating-point registers can be used by any of the
processor states.
• The Interrupt Status register is a 32-bit register. A separate register
is provided for each of the four processor states.
The format of each Interrupt Status register is as follows:
00000000
0 2 3 5 6 7 8 11 12 13 14 15 16 31
Bit Positions 0 through 2 contain the interrupt state identifier. When
an interrupt occurs, the number of the processor state being interrupted is
stored in this field of the processor state being initiated as given in table 5.
Table
S.
Interrupt State Identifier Codes
151 Definition
000 p
4
was interrupted.
001 p
3
was interrupted.
010
P2
was interrupted.
011 PI was interrupted.
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