Condition Code Utilization; Interrupt Action - RCA 70/46 Reference Manual

SS Format
(Cont'd)
CONDITION CODE
UTILIZATION
INTERRUPT ACTION
Address Error
Addressing
Specification
Protection
Data Error
Logical
Instructions
the second operand address, the contents of the general register specified
by B2 are added to the contents of the D2 field. The length of the second
operand is the same as the length of the first.
The use of a zero in the X 2 , B
1 ,
or B2 field of any instruction indicates
that no register is to be used as a component of the instruction. Instructions
may use a general register for both address modification and operand
location. Addresses are always modified before an instruction is executed.
• The condition code is set as a result of using most of the logical instruc-
tions. The condition code setting has a different meaning when using
different instructions and can be tested by subsequent branch on condi-
tion instructions for decision making. Altogether, there are six types
of result meanings. The instructions which cause the condition code to be
set and the meaning of the setting are as follows:
Condition Code Setting
Instruction
0
1
2
3
AND Zero
Not Zero
--
--
Compare Logical Equal
Low
High
--
Edit
Zero
<
Zero
>
Zero
--
Edit and Mark Zero
<
Zero
>
Zero
- -
Exclusive OR Zero Not Zero
-- - -
OR
Zero Not Zero
--
One
Test Under Mask Zero
Mixed
--
--
Translate and Test
Zero Incomplete
Complete
--
Test and Set Zero
One
- - - -
• The following interrupt conditions can occur as a result of logical
instructions:
• An address error interrupt occurs when an address specifies a loca-
tion outside the available memory. At the point of error the operation is
terminated. The result data and condition code, if affected, are
un predictable.
• An address error interrupt occurs when a full-word operand is not
located on a word boundary in a storage-to-register operation, or when an
odd register is specified as the first register in an instruction which per-
forms an operation on an even/odd pair of general registers. The operation
is suppressed.
• An address error interrupt occurs when the storage key and the protec-
tion key of the result location do not match. The operation is suppressed
and the condition code, registers, and main memory are unaltered. The
variable-length memory-to-memory instructions are the only exception,
in which case the operation is terminated and the result data and the
condition code setting are unpredictable. (This interrupt can only occur
if the memory protect feature is installed.)
• A data error occurs if a digit code of the second operand in the Edit
instruction or Edit and Mark instruction is invalid. The operation is
terminated, and the result data and condition code setting are unpredictable.
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