Si Format; Ss Format - RCA 70/46 Reference Manual

Shift Instructions
Branching Instructions
Load/Store Multiple
Instructions
SI FORMAT
SS FORMAT
Instruction Formats
• The contents of the general register specified by Rl is the first operand.
The contents of the general register specified by B2 are added
to
the D2
field. The sum specifies the number of bits of shifting to be done by the
shift operation. The
R3
field is ignored.
• The contents of the general register specified by Rl is the first operand.
The contents of the general register specified by B2 are added to the D2
field to obtain the branch address. 'The contents of the general register
specified by
R3
is the third operand.
• The
Rl
and
R3
fields specify the general register boundaries. The con-
tents of the general register specified by B2 are added to the D2 field to
obtain the main memory address of the second operand.
• The contents of the general register specified by Bl are added to the
contents of the Dl field to obtain the address of the first operand. The
second operand is the immediate eight-bit byte in the 12 field of instruction.
Op Code
o
7 8
15 16 19 20 31
• The contents of the general register specified by Bl are added to the
contents of the Dl field to obtain the address of the leftmost byte of the
first operand. The Ll field specifies the number of additional bytes in
the operand that are to the right of the first operand address. To obtain
the second operand address, the contents of the general register specified by
B2 are added to the contents of the D2 field. The L2 field specifies the
number of additional bytes in the operand that are to the right of the
second operand address. The L field specifies the number of additional
bytes that are to the right of the first and the second operand address.
I
Op Coo.
I
L, L L,
I
B,
I
o
7 8 11 12 15 16 19 20 31 32 35 36
47
Notes •
1.
A zero appearing in the X 2 , Bl or B2 fields indicates an absence of
the corresponding address or shift-amount component. An instruc-
tion can specify the same general register both for address modi-
fication and for operand location.
2. Address modification is completed before the execution of an
operation.
3. The results replace the first operand (except in Store Character
instruction, where the result replaces the second operand).
4. A variable-length result is never stored outside the field specified
by the address and length.
5. The contents of all registers and main memory locations not speci-
fied by an instruction remain unchanged except for the Edit and
Mark instruction and the Translate and Test instructions. These
instructions automatically use certain general registers as given
in table 2.
10