Add Logical
(ALR) (AL)
General Description
Format
(RR)
(RX)
Condition Code
Interrupt Action
Fixed-Point
Instructions
•
The operand specified by the second address (R 2 or X 2 /B 2 /D 2 ) is
logically added (32-bit unsigned) to the operand specified by the first
address (R
1 ) .
The sum is placed in the general register specified by the first
address. The condition code is determined by the relation of the sum
to a zero number and the occurrence of a carry out of the sign bit
position. An overflow on such carries is not recognized and does not set an
interrupt condition.
I
(ALR)
IE
Rl
R2
0
7 8
11
12
15
I
(ALl 5E
Rl
X 2
0
7 8
11
12
15 16
•
0 - sum is zero and no carry.
1 - sum is not zero and no carry.
2 - sum is zero with a carry.
3 - sum is not zero with a carry.
•
Address error:
Addressing (RX format).
Specification (RX format).
B2
D2
19 20
31
Notes
•
1.
All 32 bits of the operands participate in the logical addition.
2. The operand specified by the second address is unaltered.
136