Special Function # 1 Load Translation Memory (Ltm) - RCA 70/46 Reference Manual

S!pecial
Function
#
1
Load Translation
Memory (LTM)
Privileged
Instructions
General Description •
The translation memory is loaded with blocks of halfwords from
memory, where the blocks are specified by a Block Address Table which is
also in memory. The location of the Block Address Table is addressed by
the low-order three bytes of the general register specified by R1. The
number of memory locations per block is given in the high-order byte
of the general register specified by R1. The number of blocks to be loaded
is specified by the low-order halfword of the general register specified by
R2. The first location of the translation memory into which an entry is
to be placed is specified by the high-order halfword contained in the general
register specified by R2.
I Code •
CO.
Format
R1 R2
0 3 4 7
Condition Code
•
Unchanged .
Interrupt Action
•
Addressing .
Power Failure.
Machine Check.
Paging Error.
Paging Queue.
Notes • 1.
The high-order byte of the general register specified by R1 contains
a count of 0-255 to specify 1-256 translation memory locations in
each of the blocks.
2. The low-order three bytes of the general register specified by R1
containing the address of the Block A:ddress Table may be either
virtual or direct as indicated by the D bit.
3. Bit positions 7 through 15 in the general register specified by R2
contains the address of 0-511 of the first location of the Translation
Table to be loaded. This may specify any location in the Translation
Table. Bit positions 0 through 6 are not used and must be zeros.
This is a program restriction only.
4. Bit positions 23 through 31 in the general register specified by R2
contains a count 0-511 specifying the number of words in the
Block Address Table 1 to 512, respectively. Bit positions 16
through 22 are not used and must be zeros. This is a program
restriction only.
92