Register Space; Rx Controller Core Registers - Xilinx Vivado MIPI CSI-2 Product Manual

Register Space

This section details registers available in the MIPI CSI-2 RX Subsystem. The address map is
split into following regions:
• MIPI CSI-2 RX Controller core
• AXI IIC core
• MIPI D-PHY core
Each IP core is given an address space of 64K. Example offset addresses from the system
base address when the AXI IIC and MIPI D-PHY registers are enabled are shown in
Table 2-6: Sub-Core Address Offsets
Notes:
1. When the AXI IIC core is not present, the MIPI D-PHY offset moves up and starts at 0x1_0000. The software driver
handles this seamlessly.
MIPI CSI-2 RX Controller Core Registers
Table 2-7 specifies the name, address, and description of each firmware addressable
register within the MIPI CSI-2 RX controller core.
Table 2-7: MIPI CSI-2 RX Controller Core Registers
Address Offset
0x00
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C
0x20
0x24
MIPI CSI-2 RX Subsystem v4.0
PG232 July 02, 2019
IP Cores
MIPI CSI-2 RX Controller
AXI IIC
MIPI D-PHY
Register Name
Core Configuration Register
Protocol Configuration
Register
(1)
Reserved
Reserved
Core Status Register
Reserved
Reserved
Reserved
Global Interrupt Enable
Register
Interrupt Status Register
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Chapter 2: Product Specification
Description
Core configuration options
Protocol configuration options
Internal status of the core
Global interrupt enable registers
Interrupt status register
Table 2-6.
Offset
0x0_0000
0x1_0000
(1)
0x2_0000
21
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