Table Of Contents - Xilinx Vivado MIPI CSI-2 Product Manual

Table of Contents

Table Of Contents2
Features4
Ip Facts4
Overview5
Sub-Core Details6
Mipi D-Phy6
Rx Controller6
Chapter 1: Overview6
Ecc/Crc Forwarding8
Vcx Support8
Axi Crossbar9
Video Format Bridge9
Pixel Packing For Multiple Data Types10
Pixel Packing For Embedded Non-Image Data Types11
Pixel Packing When Video Format Bridge Is Not Present11
Axi Iic12
Applications12
Unsupported Features13
Licensing And Ordering13
License Checkers13
License Type13
Chapter 2: Product Specification14
Standards14
Performance14
D-Phy Latency15
Mipi Csi-2 Rx Controller Latency16
Video Format Bridge (Vfb) Latency16
Port Descriptions17
Resource Utilization17
Register Space21
Rx Controller Core Registers21
Core Configuration Register24
Protocol Configuration Register25
Core Status Register25
Global Interrupt Enable Register26
Interrupt Status Register26
Incorrect Lane Configuration28
Stream Line Buffer Full28
Control Error/Escape Entry Error/Escape Ultra Low Power Mode/Stopstate29
Sot Error29
Sot Sync Error29
Ecc 2-Bit Error/1-Bit Error29
Vc Mapping30
Unsupported Data Type30
Frame Synchronization Error30
Frame Level Error30
Interrupt Enable Register31
Generic Short Packet Register32
Vcx Frame Error Register32
Clock Lane Information Register34
Lane N Information Registers34
Image Information 1 Registers (Vc0 To Vc15)35
Image Information 2 Registers (Vc0 To Vc15)35
Axi Iic Registers35
Mipi D-Phy Registers36
Shared Logic37
Chapter 3: Designing With The Subsystem37
General Design Guidelines37
Shared Logic In The Subsystem39
Shared Logic Outside Subsystem39
I/O Planning42
Clocking44
Subsystem Clocks44
Clocking Structure45
Resets47
Protocol Description48
Programming Sequence48
Address Map Example48
Axi Iic Ip Core Programming48
Mipi Csi-2 Rx Controller Core Programming49
Active Lanes Configuration49
Customizing And Generating The Subsystem51
Chapter 4: Design Flow Steps51
Board Tab52
Configuration Tab53
Shared Logic Tab55
Pin Assignment Tab57
User Parameters59
Constraining The Subsystem60
Device, Package, And Speed Grade Selections60
Clock Management60
Banking61
I/O Standard And Placement61
Simulation62
Synthesis And Implementation62
Chapter 5: Application Example Design63
Application Example Design Overview63
Setup Details65
Hardware Setup65
Running The Design On The Hardware69
Implementing The Example Design70
Known Issues77
Hardware Validation78
Appendix A: Verification, Compliance, And Interoperability78
Appendix B: Debugging81
Finding Help On Xilinx.com81
Debug Tools82
Hardware Debug83
Interface Debug84
Axi4-Stream Interfaces85
Sideband Information On Axi4-Stream Interfaces85
Appendix C: Additional Resources And Legal Notices87
Xilinx Resources87
Documentation Navigator And Design Hubs87
References88
Revision History89
Please Read: Important Legal Notices90